By Topic

Test Conference, 1989. Proceedings. Meeting the Tests of Time., International

29-31 Aug. 1989

Filter Results

Displaying Results 1 - 25 of 138
  • International Test Conference 1989. Proceedings. Meeting the Tests of Time (Cat. No.89CH2742-5)

    Publication Year: 1989
    Request permission for commercial reuse | PDF file iconPDF (28 KB)
    Freely Available from IEEE
  • Standard testability bus-an applications example

    Publication Year: 1989
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (93 KB)

    Summary form only given. The standard testability bus may be implemented in a variety of ways according to the requirements of each specific application. The author describes the application of a standard testability bus to the design of a next-generation automatic test system. The approach selected was protocol independent and could thus support any combination of boundary scannable, VHSIC, and c... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Detection of transient faults in microprocessors by concurrent monitoring

    Publication Year: 1989
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (61 KB)

    Summary form only given. A novel approach, called concurrent processor monitoring for on-line detection of transient faults, that attempts to achieve high error coverage with small error detection latency is proposed. The concept of the execution profile of an instruction is defined and is used for detecting control flow and execution errors. To implement this scheme, a watchdog processor is desig... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Redundancies and don't cares in sequential logic synthesis

    Publication Year: 1989, Page(s):491 - 500
    Cited by:  Papers (11)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (780 KB)

    The authors explore the relationships between redundant logic and don't care conditions in sequential circuits. Stuck-at faults in a sequential circuit may be testable in the combinational sense but may be redundant because they do not alter the terminal behavior of a nonscan sequential machine. These sequential redundancies result in a faulty state transition graph (STG) that is equivalent to the... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Test and design for testability of reconvergent fan-out CMOS logic networks

    Publication Year: 1989
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    The authors address the robustness of adjacent vector sequences in irredundant RFO (reconvergent fan-out) logic networks made up of primitive CMOS (NAND, NOR) and fully complemented MOS (FCMOS) gates. RFO structures in which these sequences are robust are defined, and a DFT (design-for-testability) method for solving the remaining problems is described. It is shown that a large percentage of stuck... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Experiments on aliasing in signature analysis registers

    Publication Year: 1989, Page(s):344 - 354
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    An effort is made to validate experimentally predictions on aliasing in signature analysis registers under the independent error model. From the experimental results it appears that the independent error model accurately predicts the probability of aliasing in signature registers. The authors also provide justification for the adoption of a more general asymmetric error model of which the former i... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fault location in repairable programmable logic arrays

    Publication Year: 1989, Page(s):679 - 685
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    In order to ensure the manufacture of large PLA (programmable logic array) chips with reasonable yield level, a design for repairable PLAs (RPLAs) was proposed in which the partially defective chips can be repaired without reconfiguring the external routing. However, before a defective chip can be repaired, the locations of the defects must be precisely identified. The author presents a fault loca... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On the design of multiple-input shift-registers for signature analysis testing

    Publication Year: 1989
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    Exact expressions for the aliasing error probability in multiple-input shift register for signature analysis testing are derived and used to obtain criteria for the optimal synthesis of signature registers. The register behavior is modeled under the assumption of statistical independence of error vectors from the circuit under test (CUT). A general solution to the resulting Markov chain is present... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A framework and method for hierarchical test generation

    Publication Year: 1989, Page(s):480 - 490
    Cited by:  Papers (26)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (864 KB)

    The authors have proposed and implemented a dynamic framework and a method for hierarchically generating test patterns from a hierarchical net list. They have shown consistent gains in CPU over the traditional gate-level implementation while maintaining identical levels of fault coverage. In generating and characterizing modules for a large and varied set of hierarchical benchmarks, the authors be... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Built in self test of the Macrolan chip

    Publication Year: 1989, Page(s):735 - 744
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    The authors describe the experience of implementing self-test in the medium access controller (MAC) chip for the Macrolan advanced fiber-optic local area network system. The CMOS chip contains approximately 35K gates and 200 logic pins, and has been designed using a semi-custom-design approach based on a parameterized cell library. The implementation of BIST (built-in self-test) for this chip has ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Signature analysis with non-linear feedback shift registers

    Publication Year: 1989, Page(s):954 - 955
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB)

    The use of nonlinear feedback shift registers (NLFSRs) in the design of signature analyzers (SAs) was investigated. It is shown that SAs with arbitrarily low values of error-escape probability and requiring less hardware than their linear feedback shift register (LFSR) counterparts are feasible and systematically realizable View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Board-level boundary-scan: regaining observability with an additional IC

    Publication Year: 1989, Page(s):182 - 189
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    The Probe, a CMOS ASIC (application-specific integrated circuit) that can be used to regain observability lost to higher gate-to-pin ratios and packaging density is described both functionally and technically. This hardware solution will allow board-level designs to look like total boundary scan. The economic feasibility depends on how rapidly present designs move forward: successful application d... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The push for test in universities

    Publication Year: 1989
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    It is noted that the increased use of application-specific integrated circuits in products is increasing the demand for courses in VLSI. It is argued that design for testability should be an integral part of these project courses. The results of an IEEE Computer Society survey of universities teaching VLSI are presented, along with some recommendations for facilitating the process of emphasizing t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A proposed benchmark unit for evaluating electronic troubleshooting expert systems

    Publication Year: 1989, Page(s):78 - 86
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    In order to establish a uniform basis for comparing and evaluating diagnostic expert systems for functional electronic troubleshooting, a real-life benchmark unit is proposed. The HP-3478P unit is essentially identical to the HP-3478A digital multimeter. The authors first outline the criteria that guided them in the selection of this unit from a wide variety of real-life units. They describe the s... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An approach to functional level testability analysis

    Publication Year: 1989, Page(s):373 - 380
    Cited by:  Papers (23)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    The authors present an approach to testability analysis applicable to circuits containing functional modules described behaviorally. They consider two types of modules-combinational modules described by binary decision diagrams and sequential modules defined by state tables. Controllability and observability measures for such modules are defined, and algorithms are developed for computing them. Th... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The analysis of parallel BIST by the combined Markov chain (CMC) model

    Publication Year: 1989, Page(s):337 - 343
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    It is shown that the simple Markov chain model used to define the parallel BIST (built-in self-test) technique (see K. Kim et al., IEEE Trans. CAD Integrated Circuits Syst., p.919-28, Aug. 1988) does not work well for state machines. Instead, a combined Markov chain (CMC) model is proposed to analyze the behavior of state machines. It is shown that the feedback loop from the state registers, as we... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 250 MHz shared-resource VLSI test system with high pin count and memory test capability

    Publication Year: 1989, Page(s):558 - 566
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    The authors describe a 250-MHz, 2048-pin, shared-resource VLSI test system which has timing accuracy up to 300 ps and a parallel algorithmic pattern generation system for embedded memory testing. A timing generation system which provides an effective deskewing scheme in a shared-resource tester is proposed. Parallel pattern generation for high-speed memory testing is introduced, and a conversion s... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Location and identification for single and multiple faults in testable redundant PLAs for yield enhancement

    Publication Year: 1989, Page(s):670 - 678
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    The authors present the basic structure of a testable and repairable programmable logic array (PLA) and the design modifications which are required for a full diagnosis and yield enhancement. The testing process is fully analyzed, and the conditions for diagnosis are presented. It is proved that identification in the presence of multiple (crosspoint, stuck-at, and bridging) faults is possible with... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On the design and test of asynchronous macros embedded in synchronous systems

    Publication Year: 1989, Page(s):838 - 845
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    The design of synchronously testable asynchronous macros is investigated. A novel implementation model which uses an explicit state register is presented. This approach makes it possible to apply scan and boundary tests to nonsynchronous VLSI systems. The state register is composed of SR (set-reset) flip-flops, which can operate in asynchronous, synchronous, and (token) scan mode. It is shown that... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Diagnostics based on faulty signature

    Publication Year: 1989
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (88 KB)

    A fault diagnostic algorithm which makes use of the information from a faulty signature is presented. The idea is to search the likely fault locations before the tests are performed. The method reduces the number of tests required to diagnose the faults with the probability of error aliasing. Such probability is always smaller than that of error detection in signature analysis. When matching tests... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Hierarchical test pattern generation based on high-level primitives

    Publication Year: 1989, Page(s):470 - 479
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    It is demonstrated that the exploitation of high-level primitives (HLPs) and, in particular, of the knowledge concerning their function in ATPG (automatic test pattern generation) leads to significant improvements in implication, unique sensitization, and multiple backtrace. Motivated by this observation and the necessity of covering all faults inside HLPs, the authors present the extension of the... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fault simulation in a pipelined multiprocessor system

    Publication Year: 1989, Page(s):727 - 734
    Cited by:  Papers (28)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    The authors describe fault simulation algorithms for the MARS hardware accelerator. Two algorithms are considered. The first, serial fault simulation, has a performance that is linear in the number of faults. Its performance is easily predictable and it takes full advantage of the true-value simulation speed of the accelerator; it is also easy to implement. The second algorithm, concurrent fault s... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parallel automated test pattern generation on the Connection Machine

    Publication Year: 1989
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (72 KB)

    The authors present an SIMD (single-instruction multiple-data) algorithm for automated test pattern generation. An effort was made to parallelize the individual steps of FAN by employing the massive parallelism of the Connection Machine. The algorithm considers one fault at a time and generates a test for it. Fine-grain parallelism is achieved by several gates within a level simultaneously doing m... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Twenty years of ATE

    Publication Year: 1989, Page(s):3 - 6
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    The author surveys 20 years in the field of ATE (automatic test equipment) after the famous `Cherry Hill' International Test Conference of 1970. The microelectronics revolution, the development of the microprocessor, and design for testability are highlighted View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Achieving ATE accuracy at gigahertz test rates: comparison of electronic and electrooptic sampling technologies

    Publication Year: 1989
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (76 KB)

    Testing devices at clock rates exceeding 50 MHz with waveform resolution below 100 ps necessitates the use of sampling methods. The current state of the art includes two radically different sampling technologies: electronic sampling (ES) utilizing a diode bridge structure and a novel electrooptic sampling (EOS) technology which uses short light pulses as the time-resolving element. The bandwidth, ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.