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Test Conference, 1989. Proceedings. Meeting the Tests of Time., International

Date 29-31 Aug. 1989

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  • International Test Conference 1989. Proceedings. Meeting the Tests of Time (Cat. No.89CH2742-5)

    Publication Year: 1989
    Request permission for commercial reuse | PDF file iconPDF (28 KB)
    Freely Available from IEEE
  • Calculating the effects of linear dependencies in m-sequences used as test stimuli

    Publication Year: 1989, Page(s):252 - 256
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    When pseudorandom patterns generated by a linear feedback shift register (LFSR) are used as test stimuli, there is always a concern about the linear dependencies within the sequence of patterns. It is possible for these linear dependencies to prevent a specific test pattern from being present in the sequence of applied patterns. These dependencies and ways to calculate their effects on a particula... View full abstract»

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  • A fundamental approach to SPC implementation

    Publication Year: 1989, Page(s):249 - 251
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB)

    The building blocks required for a profitable statistical process control (SPC) system include adequate training, productive problem solving, and practical visibility. In addition, each SPC project must be designed to provide useful and timely data to serve the needs of the manufacturing and design organizations. As a process evolves from concept through implementation to a stable process under st... View full abstract»

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  • Design assurance in a university setting

    Publication Year: 1989, Page(s):247 - 248
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB)

    It is argued that VLSI design assurance in a university setting requires developing an environment in which a multiplicity of reliable designs can be produced by inexperienced designers at minimal costs. Two issues in design verification and testing are examined: the first relates to design for testability; the second is the practical verification of designs once they are implemented in silicon. I... View full abstract»

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  • Fault diagnosis in analogue circuits using AI techniques

    Publication Year: 1989, Page(s):118 - 123
    Cited by:  Papers (15)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    The authors describe a technique for detecting and locating faults in analogue circuits by checking that the measurements are consistent with the circuit function. The unique representation used accommodates the imprecise nature of analogue circuits. A model of the circuit is formed from the constraints imposed by the behavior of the components and the interconnections. The values of parameters wi... View full abstract»

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  • The push for test in universities

    Publication Year: 1989
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    It is noted that the increased use of application-specific integrated circuits in products is increasing the demand for courses in VLSI. It is argued that design for testability should be an integral part of these project courses. The results of an IEEE Computer Society survey of universities teaching VLSI are presented, along with some recommendations for facilitating the process of emphasizing t... View full abstract»

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  • Fast accurate and complete ADC testing

    Publication Year: 1989, Page(s):111 - 117
    Cited by:  Papers (38)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    It is noted that the development of monolithic ADCs (analog-to-digital converters) dictates `all codes' testing to guarantee specifications. An on-the-fly method of analyzing ADC outputs using specialized hardware is described. This method provides immediate availability of full INL and DNL (integral and differential nonlinearity) characteristics. The noise sensitivity of the standard method is co... View full abstract»

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  • Design and test in the universities

    Publication Year: 1989
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (76 KB)

    It is argued that a broad-based VLSI curriculum should be established in the university. In conjunction with theoretical teaching, facilities that include an integrated design and test environment, CAD tools, and ATE (automatic test equipment) should be provided. A possible program might be directed toward the computer (or electrical) engineering degree with emphasis on VLSI design and testing. Th... View full abstract»

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  • Topological testing

    Publication Year: 1989, Page(s):103 - 110
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    Topological testing is introduced and its applications are presented. Topological testing uses graph-theoretic optimization methods such as the traveling salesman problem, the Chinese postman problem, coloring, path covering, and partitioning to minimize the test time. The topological testing techniques can be applied to test a system's behavior and its organization at each level of the system's h... View full abstract»

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  • Engineering curricular for `meeting the tests of time'

    Publication Year: 1989, Page(s):242 - 244
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    The authors describe a background study, course developments, and concepts for a curriculum in electronics test engineering. Their conclusion is that appropriate academic programs in electronics test engineering should be developed at the B.S., M.S., and Ph.D levels. The identification of the common background and education, as well as the implementation, of these programs requires strong universi... View full abstract»

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  • CAE functionality for verification of diagnostic programs

    Publication Year: 1989, Page(s):94 - 102
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (700 KB)

    A feasibility study that has identified computer-aided engineering (CAE) features and a methodology approach that will support BIT (built-in-test) verification through fault simulation are described. With an example, the authors illustrate the evolutionary fault simulation features and the attendant methodology to support BIT verification by simulation. The simulator functionality and methodology ... View full abstract»

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  • Mixed-mode simulation for time-domain fault analysis

    Publication Year: 1989, Page(s):231 - 241
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (816 KB)

    The issue of testing mixed-mode (analog-digital) ASICs (application-specific integrated circuits) is considered. The author describes a uniform mixed-mode simulation environment which allows a selection of the level of modeling for both analog and digital macros and includes and implementation involving the concurrent operation of hardware accelerators for both analog and digital simulation. In ad... View full abstract»

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  • Transmission line simulation for testing ISDN devices

    Publication Year: 1989, Page(s):87 - 93
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    A transmission line model has been developed to simulate the effects of sourcing ISDN (integrated services digital network) waveforms through twisted-pair telephone cable. Circuit simulation models for three different wire gauges have been used to predict the transmission characteristics of arbitrary networks using SPICE simulations. These models have been configured to simulate a standard test ne... View full abstract»

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  • Methods of test waveform synthesis for high speed data communication devices

    Publication Year: 1989, Page(s):222 - 230
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    When testing ISDN (integrated services digital network) and other high-data-rate communications devices, stimulus waveforms will often emulate signals that a device under test (DUT) will process in its final application. When conventionally architected digital-signal-processor-based instrumentation is used to provide these waveforms, there exist test conditions which can easily overburden machine ... View full abstract»

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  • Main frame diagnosis support system

    Publication Year: 1989, Page(s):283 - 289
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    The authors have developed an automatic system called CONDOR (concurrent error checker diagnosability analyzer) which quantitatively evaluates the effectiveness of the arrangement of error detection circuits and automatically generates a fault dictionary based on the computer logic design data file. The CONDOR diagnosis support was applied to a large-scale logic computer with more than a million g... View full abstract»

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  • Reconfigurable resource architecture improves VLSI tester utilization

    Publication Year: 1989, Page(s):597 - 604
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    A VLSI tester which can be reconfigured from one high pin count test head to multiple independent lower pin count test heads is described. This reconfigurable resource architecture is shown to provide improved tester utilization for the factory. Greater utilization results in reduced capital equipment costs, thus reducing test costs for the test equipment user. A reconfigurable resource architectu... View full abstract»

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  • ESSENTIAL: an efficient self-learning test pattern generation algorithm for sequential circuits

    Publication Year: 1989, Page(s):28 - 37
    Cited by:  Papers (41)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (772 KB)

    The authors present ESSENTIAL, deterministic automatic test pattern generation algorithm for sequential circuits. By combining reverse time processing over time frames and forward processing within time frames, ESSENTIAL avoids the detrimental a priori determination of a topological path to be sensitized or of a primary output, to which the fault effects have to be propagated. Moreover, the propos... View full abstract»

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  • A proposed benchmark unit for evaluating electronic troubleshooting expert systems

    Publication Year: 1989, Page(s):78 - 86
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    In order to establish a uniform basis for comparing and evaluating diagnostic expert systems for functional electronic troubleshooting, a real-life benchmark unit is proposed. The HP-3478P unit is essentially identical to the HP-3478A digital multimeter. The authors first outline the criteria that guided them in the selection of this unit from a wide variety of real-life units. They describe the s... View full abstract»

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  • A telecommunications line interface test system architecture

    Publication Year: 1989, Page(s):216 - 221
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    The authors present new test techniques which have been used to develop a high-quality, cost-efficient test module suitable for high-volume testing of T1/PCM-39 line interface devices. This test module is capable of fully testing the key parameters of sophisticated line interface driver/receivers (jitter tolerance, jitter attenuation, and pulse-shape template conformance). Using this module, a 75%... View full abstract»

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  • A self-test system architecture for reconfigurable WSI

    Publication Year: 1989, Page(s):275 - 282
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    Progress in wafer scale integration (WSI) has brought the problem of electronic system testing into the semiconductor manufacturing arena. The problem is complicated by the reduced controllability and observability implicit at the full wafer integration level. Structured methods must be employed to generate and apply tests in a hierarchical fashion at the function, chip, and system levels. The aut... View full abstract»

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  • Delay test generation for synchronous sequential circuits

    Publication Year: 1989, Page(s):144 - 152
    Cited by:  Papers (55)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (808 KB)

    The author presents a method for generating test sequences to detect delay faults in sequential circuits using the stuck-at-fault sequential test generator STALLION. The method is complete in that it will generate a delay test sequence for a targeted fault given sufficient CPU time, if such a sequence exists. Faults for which no delay test sequence exists are termed sequentially delay redundant. T... View full abstract»

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  • A testing technique to characterize E2PROM's aging and endurance

    Publication Year: 1989, Page(s):391 - 396
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    The authors present a testing method for monitoring E2PROM (electrically erasable programmable ROM) cell aging. The technique is not based on any particular assumption about cell technology: hence it can be used to characterize wearout dynamics in all cases in which charge trapped in tunnel oxide is the main failure mechanism. The method is validated by means of a wide set of measuremen... View full abstract»

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  • Testability analysis of synchronous sequential circuits based on structural data

    Publication Year: 1989, Page(s):364 - 372
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    Test sequence length is an effective measure of testability of a sequential circuit. The lower the bound on the length, the more testable the circuit is. A graph-theoretic approach is used to compute the bound on test sequence length for any sequential circuit. The condensation of the graph is found by collapsing the strongly connected components into single nodes. By analyzing each stem region, i... View full abstract»

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  • The analysis of parallel BIST by the combined Markov chain (CMC) model

    Publication Year: 1989, Page(s):337 - 343
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    It is shown that the simple Markov chain model used to define the parallel BIST (built-in self-test) technique (see K. Kim et al., IEEE Trans. CAD Integrated Circuits Syst., p.919-28, Aug. 1988) does not work well for state machines. Instead, a combined Markov chain (CMC) model is proposed to analyze the behavior of state machines. It is shown that the feedback loop from the state registers, as we... View full abstract»

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  • A high performance, 10-volt integrated pin electronics driver

    Publication Year: 1989, Page(s):846 - 853
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    A high-voltage process module is added to a standard 1.5-μm digital CMOS process, allowing a 10-volt pin electronics driver to be integrated onto the same silicon with its timing and formatting circuitry. A single analog output driver circuit provides fast rise time, low-distortion output waveforms for both narrow and wide voltage swings, eliminating the need for dual drivers or testheads when ... View full abstract»

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