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ASIC/SOC Conference, 2002. 15th Annual IEEE International

Date 25-28 Sept. 2002

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Displaying Results 1 - 25 of 89
  • Proceedings 15th Annual IEEE International ASIC/SOC Conference (Cat. No.02TH8626)

    Publication Year: 2002
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    Freely Available from IEEE
  • Author index

    Publication Year: 2002 , Page(s): 0_17 - 0_18
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    Freely Available from IEEE
  • Virtual in-circuit emulation for timing accurate system prototyping

    Publication Year: 2002 , Page(s): 49 - 53
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (434 KB) |  | HTML iconHTML  

    This paper presents a novel HW/SW verification methodology called virtual in-circuit emulation, that is suitable for a platform-based design paradigm, where the main objective of co-verification is to validate the interaction between an existing core processor and some application-specific peripheral system. The proposed co-verification solution shares with conventional emulation schemes the possibility of performing both functional and timing-accurate validation with the same accuracy of the hardware, and greater speed than simulation software, yet it achieves this at a minuscule fraction of the cost of a conventional emulation system. We have validated the virtual in-circuit emulation paradigm on a real board hosting an ARM core and various hardware peripherals running an embedded application, that has been interfaced to a custom-designed I/O unit for the acquisition of data samples, described in SystemC. View full abstract»

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  • A CMOS Miller hold capacitance sample-and-hold circuit to reduce charge sharing effect and clock feedthrough

    Publication Year: 2002 , Page(s): 92 - 96
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (359 KB) |  | HTML iconHTML  

    A technique using Miller capacitance in the sample-and-hold (S/H) circuit is introduced in this paper to reduce the charge sharing effect (CSE) due to the parasitic capacitance and clock feedthrough from a sampling switch. A compact cascode amplifier is used in the Miller feedback circuit and a ten times reduction in CSE and clock feedthrough is achieved. The S/H capacitor is split into two parts, Csh1 and Csh2. One of these S/H capacitors effectively reduces the CSE while the other capacitor reduces clock feedthrough. View full abstract»

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  • An effective soft module floorplanning algorithm based on sequence pair

    Publication Year: 2002 , Page(s): 54 - 58
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (386 KB) |  | HTML iconHTML  

    An effective soft module floorplanning algorithm is proposed. It uses simulated annealing framework based on the sequence pair representation. Because a soft module may have many possible shapes, so it will take long time to find a good solution in simulated annealing method. We proposed a method which finds four candidates of module shape to be chosen in a simulated annealing process for each module. These candidates provide a better choice toward local optimal packing. We combine our method with a fast sequence pair evaluation algorithm and keep the same time complexity nlogn of a sequence pair evaluation. During the simulated annealing process, it either chooses to change the shape of one module or to swap the modules in the sequence pair. We have implemented this algorithm. For all MCNC benchmark soft module floorplanning problems, we have obtained more compact floorplan with much less run time comparing to a previous work . For example, for the MCNC benchmark ami49, our algorithm obtained 0.48% of dead space in 142 seconds using a 440 MHz Ultra10 workstation. The previous work to Lagrangian relaxation approach obtained 7.7% of dead space and 2354 seconds using a 600 MHz Pentium III processor. View full abstract»

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  • Design of an integrated silicon connectionist retina

    Publication Year: 2002 , Page(s): 133 - 136
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (359 KB) |  | HTML iconHTML  

    We present here a new paradigm based on a centralized architecture to realize electronic artificial retina. This original architecture, named connectionist retina, can execute in real time RBF (radial basis function) and MLP (multilayer perceptron) neural network applications. We demonstrate that this intelligent embedded system could be used for vision applications. We describe the realized prototype system. View full abstract»

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  • Split accumulator with phase modulation for high speed low power direct digital synthesizers

    Publication Year: 2002 , Page(s): 97 - 101
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB) |  | HTML iconHTML  

    A new split accumulator architecture to be used in direct digital frequency synthesizer (DDS) systems is presented in this paper. This new design takes into consideration that only part of the accumulator output is used to address the sine wave mapping. The most significant bits of the accumulator drive the mapping block and need to be updated on every sampling clock, while the least significant bits are not visible to the rest of the design and can be updated less frequently. Also the phase modulation adder is moved to the front of the accumulator. Benefits of the proposed architecture are fewer constraints in implementation, reduced power consumption of 40% (estimation) compared to standard approaches, and less area with no degradation in terms of spurious-free dynamic range (SFDR) performance. View full abstract»

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  • Influence of MPEG-4 parameters on system energy

    Publication Year: 2002 , Page(s): 137 - 142
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (426 KB) |  | HTML iconHTML  

    The impact of MPEG-4 video coding algorithms and their parameters on total energy (communication plus computation) is investigated. Specifically, the effect of the quantization parameter, number of B-frames, error-resilience techniques, content-based coding, and spatial and temporal scalability options are studied. Based on the simulation results, recommendations are made for the choice of these algorithms and their parameters such that total energy minimization is achieved. During this process, the residual battery energy of a mobile device and the state of the wireless link are also considered. We believe that the results and recommendations presented in this paper could be a useful step towards designing low power wireless multimedia networks that involve video transmission in general and employ MPEG-4 in particular. View full abstract»

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  • Fast system-level design space exploration for low power configurable multimedia systems-on-chip

    Publication Year: 2002 , Page(s): 150 - 154
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (418 KB) |  | HTML iconHTML  

    In this paper, we present a methodology to perform a very fast system-level design space exploration of parameterized multimedia architectures. The methodology is applied to a functional model of a wireless multimedia platform developed by Accent. Our approach guarantees the correctness of the dataflow and finds pareto-optimal solutions by considering area, performances and power consumption. The implementation of an earliest deadline first-like arbitration policy achieves a very efficient scheduling of bus requests, whereas the architecture can be re-configured in terms of run-time in order to optimize power consumption dynamically. The results of applying this design methodology to an industrial project are presented. View full abstract»

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  • Adaptive PRML SOC development for read/write capable optical drives

    Publication Year: 2002 , Page(s): 102 - 106
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (353 KB) |  | HTML iconHTML  

    A new PRML (partial response maximum likelihood) architecture is presented to demonstrate its high-speed operation - 420 MHz for DVD-ROM 16X - and read/write capabilities in optical systems - CD-R/RW, DVD-R/RW, DVD-RAM. In order to realize 420 MHz operation, and maximize the channel data recovery capability, new data and clock recovery methods are proposed. In this paper, the performance of the data recovery parts are mostly described. The adaptive PRML LSI has three times better performance than conventional slicer systems in sync error tests. Also, the PID (physical ID) test yields a 2 times lower rate on the byte error test. Finally, the playback performance for poor quality DVD movie titles is increased by around 70% with the PRML system. A test chip was fabricated using 0.18 μm CMOS technology and the product has been proved to demonstrate the performance of the proposed architecture. View full abstract»

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  • System-on-a-chip global interconnect optimization

    Publication Year: 2002 , Page(s): 399 - 403
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (411 KB) |  | HTML iconHTML  

    The width of global interconnects is optimized to have a large bisectional bandwidth along with a small latency, power dissipation, repeater area and via blockage. The optimal wire width, which maximizes the product of data flux density OD and reciprocal delay 1/τ, is independent of the interconnect length and can be used for all global interconnects. Data flux density OD (per unit width) determines the bisectional bandwidth and therefore, the total number of bits per second that global interconnect levels can potentially transfer. Using optimal wire width decreases the latency, energy dissipation, and repeater area by 42%, 30%, and 84%, respectively compared to using half the optimal wire width at the price of 14% smaller bisectional bandwidth. View full abstract»

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  • An 8-bit 200 MS/s CMOS folding/interpolating ADC with a reduced number of preamplifiers using an averaging technique

    Publication Year: 2002 , Page(s): 80 - 83
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (292 KB) |  | HTML iconHTML  

    An 8-bit 200 MSample/s CMOS folding/interpolating ADC chip was implemented by using a 0.35-μm double-poly CMOS process. The number of preamplifiers was reduced to half by using an averaging technique with a resistor array in comparison with the published folding/interpolating ADC chips. The delay time of digital encoder block was reduced to 1.3 ns from 2.2 ns by using a DCVSPG-style differential logic. The chip area and the measured power consumption were 1.02 mm2 and 120 mW respectively at the supply voltage of 3.3 V. View full abstract»

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  • Realization of compact low-power ripple-flash A/D converter architectures using conventional digital CMOS technology

    Publication Year: 2002 , Page(s): 71 - 74
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (334 KB) |  | HTML iconHTML  

    In this paper, we present a generalized approach for the construction of ripple-flash ADC architectures that consist of cascade-connected capacitive threshold gates, realized using conventional CMOS technology. The main advantages of the proposed ADC architecture are the very small layout area, simple operation, high input-to-output response speed, and very low power dissipation. A new differential output voltage comparator is presented to ensure high precision and low propagation delay times. Several different ADC implementations are explored, including 4-bit, 5-bit and 6-bit ripple-flash circuit that demonstrate highly accurate DC transfer characteristics with INL errors smaller than 0.1 LSB, and near-ideal SNR levels for sampling frequencies of up to 50 MHz. Test circuits manufactured with 0.8 μm CMOS technology have shown that sampling rates in excess of 50 MHz are possible with this approach, while the silicon area and the power dissipation of the tested ADC circuits remain at least one order of magnitude smaller than those of similar flash ADCs built with the conventional approach. View full abstract»

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  • A spread spectrum based communication system for an integrated sensor microsystem

    Publication Year: 2002 , Page(s): 336 - 340
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (386 KB) |  | HTML iconHTML  

    This paper describes the design and implementation of a spread spectrum based miniaturized communication system for an integrated sensor microsystem, to be implemented as part of a system-on-chip device. One of the most important tasks in such a system is to convey information reliably on a multiple access based environment. In addition to the minimization of interferences, the devices have strict power and area limitations. The paper describes the application environment, the choice of the communication protocol, and the implementation of the transmitter and receiver circuitry. We provide results using practical sensor data which demonstrate satisfaction of functionality, area, and power constraints even when a degree of programmability is incorporated into the transmitter. View full abstract»

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  • Scaled accumulation FETs for ultra-low power logic

    Publication Year: 2002 , Page(s): 371 - 375
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (334 KB) |  | HTML iconHTML  

    Ultra-low power systems require very low standby power and operate at moderate speeds. Traditionally, the normal surface channel inversion (SCI) FET would be considered better for such applications when compared to the buried channel (BC) FET, since the BC FET has always shown more short channel effects in past research. However, past comparisons between the two FETs have been done with the highest frequency in mind and the same conclusion need not hold true for moderate speed, ultra-low power applications. Due to a better subthreshold slope and negligible band to band tunneling leakage at the drain-halo and drain-channel region, the BC FET is better suited for such applications. View full abstract»

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  • Extending scaling theory by adequately considering velocity saturation

    Publication Year: 2002 , Page(s): 145 - 149
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (369 KB) |  | HTML iconHTML  

    This paper addresses the problem of comparing the performance and the area and power consumption of integrated circuits built in different technologies. In the literature there are several methods described but these do not sufficiently take the velocity saturation into account. They either ignore velocity saturation or assume the device is always in velocity saturation. The approach presented in this paper handles the effects of velocity saturation more adequately. View full abstract»

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  • Power management of the autonomous error-tolerant cell

    Publication Year: 2002 , Page(s): 109 - 113
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (457 KB) |  | HTML iconHTML  

    This article presents a power management scheme for a new circuit concept - the autonomous error-tolerant (AET) cell - the inner functionality, interconnectivity and reconfiguration of which have been presented earlier. In order to meet reliability and energy efficiency objectives, a special power management strategy and implementation of this strategy are proposed. The power management system consists of power switches, a charge pump for a high voltage generation (for EEPROM cells) and a power management unit (PMU) for regulating and monitoring. The first part of the power management strategy focuses on the functionality of the power management system: we explain the function of power switches and assign design rules for them, propose a solution for high voltage generation, and present the basic blocks and functionality of the PMU. The second part of the strategy concentrates on the power distribution: different power distribution network topologies are used in different regions of the cell. The important aspect when designing the distribution strategy is the effect of power supply noise on the cell performance. Finally, we present the results for power supply noise analysis based on the estimates for silicon area and power consumption in the digital core (DC) of the AET cell in 0.18 μm technology. View full abstract»

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  • Low-voltage current-mode analog circuit structures and their applications

    Publication Year: 2002 , Page(s): 477 - 478
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (253 KB)  

    First Page of the Article
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  • System-level power evaluation of an embedded software data block processing algorithm

    Publication Year: 2002 , Page(s): 451 - 455
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (450 KB) |  | HTML iconHTML  

    Data block processing algorithms have demonstrated significant efficiency in terms of low power consumption when applied to mainly hardware implementation of digital signal processing algorithms. In this paper, a generic data block processing algorithm is applied to the implementation of an FIR filter on a system-on-chip platform incorporating a micro controller and a programmable 32 bit DSP processor. The block processing algorithm is evaluated at the system-level including the performance metrics speed, energy, power and area. The data block processing technique achieves a reduction in energy consumption of 18% and memory accesses are reduced by 44%, for an 8 tap FIR filter. Our algorithm is targeted as a macro block, which can be re-used in the design of more complex DSP systems on the SoC platform. View full abstract»

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  • Architecture and implementation of an embedded reconfigurable logic core in CMOS 0.13 μm

    Publication Year: 2002 , Page(s): 3 - 7
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (446 KB) |  | HTML iconHTML  

    Reconfigurable logic is gaining importance in the context of embedded systems. But cost-efficient architectures implementable in standard CMOS technology, and mature design and mapping tools for them are still missing. This paper presents a novel architecture of an embedded reconfigurable logic (RL) core optimised for DSP applications. Tuning towards the application domain allowed one to reduce the logic cell implementation cost and the logic cell routing resources by 23% and 28%, respectively, compared to a commercial FPGA device with equivalent functionality. A tile-based approach which enabled the implementation of the RL core at a reduced design effort is also described. Finally, some VLSI implementation details of the core and the test chip realised in a standard 0.13 μm CMOS process technology are discussed. View full abstract»

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  • Impact of technology scaling and packaging on dynamic voltage scaling techniques

    Publication Year: 2002 , Page(s): 244 - 248
    Cited by:  Papers (3)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (410 KB) |  | HTML iconHTML  

    This paper studies how the effectiveness of various dynamic voltage scaling mechanisms is affected by technology scaling and system activity. We show that Vdd scaling maintains its effectiveness while Vth scaling and supply gating become more efficient as the feature size decreases. We also discuss the impact of packaging and. provide tools for bringing it early into the design process. In this way, short-term and long-term savings are identified, with the latter providing additional energy savings up to 10.2%, on average. View full abstract»

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  • Design of transport triggered architecture processor for discrete cosine transform

    Publication Year: 2002 , Page(s): 87 - 91
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (421 KB) |  | HTML iconHTML  

    The trend in programmable architectures for digital signal processing is to move towards high-level language programming and customizable architectures. Several design methodologies have been proposed for designing application-specific instruction-set processors (ASIP) where the hardware resources are tailored according to the requirements of the application. This paper describes the design of an ASIP for a 32-point discrete cosine transform using the tools from the MOVE framework, which is a semi-automatic design methodology for designing processors that utilize the paradigm of transport triggered architecture. Estimations of the designed processor are obtained on program execution, code size, timing and area. View full abstract»

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  • Design of broadband controller for residential gateway applications

    Publication Year: 2002 , Page(s): 283 - 287
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (393 KB) |  | HTML iconHTML  

    As Internet technology becomes more pervasive, homes are getting connected to cable or DSL. The increasing user demands for "always on" service along with multiple connectivity for voice and data is gradually making the presence of a residential gateway in every household a reality. A residential gateway should have routing and bridging capabilities along with seamless connectivity to contemporary premise networking technologies. Integration of all these features on a single device essentially requires a rich architecture, smart design techniques and thorough verification. This paper describes the architecture and design of a broadband network controller which is a critical component of TI's voice and data centric residential gateway solution. View full abstract»

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  • A compact model for projections of future power supply distribution network requirements

    Publication Year: 2002 , Page(s): 376 - 380
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB) |  | HTML iconHTML  

    A closed-form worst-case IR drop model is developed to enable projections of the wiring resource requirements of the power supply distribution networks of future microprocessors and ASICs. The model is then used to highlight the design trade-off between I/O requirements and global wiring area needed for power distribution across three generations. For the 2013 technology generation, the global wiring resources exceed 40% of the available if fewer than 10,000 I/Os are utilized for power and ground. View full abstract»

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  • On-chip interconnects for next generation system-on-chips

    Publication Year: 2002 , Page(s): 211 - 215
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (461 KB) |  | HTML iconHTML  

    Today's deep submicron fabrication technologies enable design engineers to put an impressive number of components like microprocessors, memories, and interfaces on a single microchip. With the emergence of 100 nm processes, billions of transistors can be integrated on one die and form a parallel system, consisting of thousands of components. To handle this impressive number of components, it is important to provide a communication infrastructure which is able to scale with the capabilities of upcoming fabrication technologies and which provides the foundation for efficient on-chip communication protocols. This paper addresses the architectural requirements which are coupled with the transfer of well known techniques from parallel computers onto the design of SoCs and proposes an on-chip architecture which is based on active switch boxes. We show that this architecture is able to fill the existing design gap between an efficient use of the design space and the design complexity, with reasonable resource requirements. View full abstract»

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