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Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International

Date 10-12 Feb. 1982

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Displaying Results 1 - 25 of 147
  • [Front cover]

    Publication Year: 1982, Page(s): f1
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  • Foreword diversity in silicon

    Publication Year: 1982, Page(s): 3
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  • Table of contents

    Publication Year: 1982, Page(s):4 - 7
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  • Session 1 device modeling and characterization [breaker page]

    Publication Year: 1982, Page(s): 11
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  • Yield model for 256K RAMs and beyond

    Publication Year: 1982, Page(s):12 - 13
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (290 KB)

    An updated yield model based on visual inspection, electrical tests, bit failure maps and failure analysis will be reported. The approach has been verified for the manufacture of 64K memories. It includes yield calculations for partially good product and redundancy and provides yield estimates for 128K and 256K chips. View full abstract»

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  • Numerical simulation of MOS capacitance for a wide range of temperatures, impurity profiles and surface state densities

    Publication Year: 1982, Page(s):14 - 15
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (443 KB)

    This report will describe a method for the numerical evaluation of the capacitance of MOS structures as a function of temperature for arbitrary impurity profiles and surface state distributions. View full abstract»

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  • A recombination model for the low current performance of submicron devices

    Publication Year: 1982, Page(s):16 - 17
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    This paper will cover a generation-recombination model which describes the influence of metallic precipitates on the current gain, leakage current, and 1/f noise of small geometry transistors. The model predicts an increase in device sensitivity to contamination as geometries are reduced to submicron dimensions. View full abstract»

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  • Drift collection of alpha generated carriers and design implications

    Publication Year: 1982, Page(s):18 - 19
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (305 KB)

    A report on the effects of alpha particles which can induce an electric field and enhance the collection of carriers will be presented. The collection has been found to be fast, efficient, directional and sensitive to bias and substrate resistivity. The impact of this mechanism on VLSI scaling, design concepts, cell structures and technology will be discussed. View full abstract»

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  • Alpha-particle-induced soft error rate modeling

    Publication Year: 1982, Page(s):20 - 21
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (333 KB)

    Monte Carlo procedures have been developed to obtain soft error rates (SER). The SER for a 1μm groundrule DRAM, due to alphas enamating from processing materials, shows the prevalence of multiple errors. SER reducing methods, using epi-layers, buried implant layers and Hi-C structures have been evaluated and found to be marginally effective. View full abstract»

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  • Session 2 digital signal processors [breaker page]

    Publication Year: 1982, Page(s): 23
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  • A 64b floating point processor

    Publication Year: 1982, Page(s):24 - 25
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (705 KB)

    A floating point chip set capable of one-million scalar operations per second will be reported. The set consists of add/subtract, multiply and divide chips. View full abstract»

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  • A 2 µ CMOS/LSI 32-point fast fourier transform processor

    Publication Year: 1982, Page(s):26 - 27
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (829 KB)

    A monolithic 2μ CMOS/LSI processor, operating on 32 complex data samples and computing 32 complete Fourier coefficients, will be described. The transform is implemented using the in-place radix decimation-in-time algorithm. View full abstract»

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  • A monolithic CMOS maximum-likelihood convolutional decoder for digital communication systems

    Publication Year: 1982, Page(s):28 - 29
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (327 KB)

    This paper will describe a device Providing forward error correction for NASA's 30/20 GHz program via a maximum-likelihood convolutional decoder with constraint length = 5, rate = 1/2 and Q = 4. View full abstract»

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  • A digital signal processing LSI

    Publication Year: 1982, Page(s):30 - 31
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (645 KB)

    A single chip signal processor for a digital MODEM (9600 or 14400 bps) will be covered. Performance has been achieved with a precision multipler and special instruction group for digital signal processing, Device is implemented with 3μ enhancement-depletion NMOS technology. View full abstract»

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  • A microcomputer with digital signal processing capability

    Publication Year: 1982, Page(s):32 - 33
    Cited by:  Papers (29)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (799 KB)

    A single microcomputer for realtime digital signal processing and high-speed controller applications, with a 200ns instruction cycle, 16 × 16 parallel multiplier, 32b arithmetic unit, 144 by 16 data memory, a 1536 by 16 program and coefficient memory, will be discussed. View full abstract»

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  • Session 3 linear circuit techniques [breaker page]

    Publication Year: 1982, Page(s): 35
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  • A 4-quadrant MOS analog multiplier

    Publication Year: 1982, Page(s):36 - 37
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (477 KB)

    A 4-quadrant MOS analog multiplier, which achieves linearity better than 0.3% at 75% of full-scale swing, a bandwidth of dc-1.5 MHz and output noise 77dB below full scale, will be reported. Active area is 450 mil2. View full abstract»

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  • Differential NMOS analog building blocks for PCM telephony

    Publication Year: 1982, Page(s):38 - 39
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (441 KB)

    This paper will discuss a family of differential NMOS analog circuits developed for CODEC/filter telephony applications. Switched capacitor filters, auto zero circuits, an encoder, output filter and various gain blocks, including a Power amplifier, will be described. View full abstract»

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  • A 4-quadrant cosine-synthesis circuit

    Publication Year: 1982, Page(s):40 - 41
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    A circuit implementing an algebraic approximation to the cosine function, valid in all four quadrants with an error of 0.6% will be described. The approximation results in a smooth, differentiable function, without slope discontinuities. View full abstract»

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  • A universal trigonometric function generator

    Publication Year: 1982, Page(s):42 - 43
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (343 KB)

    A synthesis principle applied to a monolithic circuit capable of generating trigonometric functions (sine, cosine, tangent, cosecant, secant and cotangent, plus arctangent) will be Presented. Analog inputs represent angle and amplitude. Law conformance is as close as ∓ 0.02%. View full abstract»

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  • A monolithic balanced modulator-demodulator for instrumentation

    Publication Year: 1982, Page(s):44 - 45
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (783 KB)

    This report will discuss a self-contained monolithic circuit, employing alternating positive and negative gain channels controlled by a voltage comparator with 200μV hysteresis. Included are 3MHz, 20V/μs switchable opamps. Gain options are adjusted by laser-wafer trimming and selected by pin strapping. View full abstract»

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  • A monolithic 8b two-step parallel ADC without DAC and subtractor circuits

    Publication Year: 1982, Page(s):46 - 47
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (792 KB)

    THE DEVELOPMENT of high-speed monolithic 8b A/D converters for digital processing of video signals has been receiving a high priority. Most designs have incorporated a flash-type ADC with 2"-1 comparators, involving complex circuitry. It has been found that this complexityc an be reduced, in general, through the use of two-step parallel A/D conversion, where local D/A converter (DAC) and subtracto... View full abstract»

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  • Session 4 formal opening of conference [breaker page]

    Publication Year: 1982, Page(s): 49
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  • Technology needs of the information age

    Publication Year: 1982, Page(s):50 - 51
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    Today, at the threshold of the information age, an accelerating change in our way of life is already apparent, a change likely to have an impact more profound than that of the industrial revolution. This transition in our society is paced by the merging of telecommunications and data processing, but a much wider range of industries will be affected. Those that respond, adapt and contribute to the ... View full abstract»

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  • Session 6 testing and design automation [breaker page]

    Publication Year: 1982, Page(s): 53
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