By Topic

Electronic Manufacturing Technology Symposium, 1989, Proceedings. Seventh IEEE/CHMT International

Date 25-27 Sept. 1989

Filter Results

Displaying Results 1 - 25 of 67
  • Seventh IEEE/CHMT International Electronic Manufacturing Technology Symposium. Proceedings 1989 (Cat. No.89CH2720-1)

    Save to Project icon | Request Permissions | PDF file iconPDF (107 KB)  
    Freely Available from IEEE
  • Mass production back-grinding/wafer-thinning technology for GaAs devices

    Page(s): 209 - 213
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (543 KB)  

    A mass-production back-grinding technology that is applicable to a fully automatic wafer-thinning process in GaAs device manufacturing is described. Excellent productivity has been realized because the brittleness of GaAs has been overcome. A mirrorlike, stress-free surface was obtained by utilizing the wafer-rotating downfeed grinding method with slight chemical etching. The thickness of the deformed layer due to back-grinding was evaluated at 0.6 mu m. the wafer bow and the changes in electrical characteristics of GaAs devices caused by this layer were eliminated by chemical etching. The threshold voltages of GaAs MESFETs were confirmed to shift negatively by no more than 5 mV. This technology has been successfully demonstrated in several kinds of GaAs device fabrication processes.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Technology transfer-a future imperative

    Page(s): 176 - 181
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (576 KB)  

    The Lehigh graduate program in manufacturing systems engineering, now in its sixth year, is described. An industrial advisory board has been enlisted with the mission of assisting the Center for Manufacturing Systems Engineering, guiding the program, and ensuring that technology transfer is accomplished both from campus into industry and from industry into the classroom. The Center for Manufacturing Systems Engineering relies heavily upon feedback from industry in structuring the research mission and assessing priorities for allocation of resources. The program emphasizes features thought to be essential in preparing manufacturing professionals for the twenty-first century View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • CALCE research opportunities at the University of Maryland

    Page(s): 182 - 185
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB)  

    The University of Maryland has initiated an integrated program in computer-aided life cycle engineering (CALCE) to assist the nation's industries in competitively meeting the foreign challenge both economically and technically. To meet current needs in electronic design, the University of Maryland established an Industry/University Cooperative Research Center whose research theme is to promote basic study in the application of advanced technologies to the engineering design of electronic equipment. The CALCE effort places special emphasis on development and optimization of those design techniques which lend themselves to intelligent manufacturing, reliability, and maintainability; multiparameter optimization, evaluation of materials, and structures in unique environments; and advanced modeling, simulation, and prediction for industrial applications. The history of this CALCE effort is reviewed, and the CALCE Center organization, facilities, and research are described View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The reliability of reflow soldering by hot air reflow

    Page(s): 43 - 47
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (244 KB)  

    The reliability of a solder joint produced on an FR-4 substrate by hot air reflow soldering in SMT (surface mount technology) was investigated. The hot air reflow method is shown to make the temperature of the mounted components and substrate equal to the ambient temperature and does not greatly damage components. The capacitance drift did not change after 700 cycles on MIL-STD-202F(107G), at -65°C to 125°C. The shear strength on the solder joint was not reduced after 700 cycles on MIL-STD-202F(107G), at -65°C to 125°C. The Engelmaier model showed better results against 700 cycles of thermal shock than the average life of the solder. The large heat capacitance eliminates fluctuation of the furnace temperature and makes the surface temperature of the substrate even to ensure overall connection reliability. A stable setting temperature profile can be attained even when a different substrate is used, making this method suitable for diversified small-quantity production View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Job disposition cost model

    Page(s): 286 - 288
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (128 KB)  

    A comprehensive cost model has been developed to evaluate product dispositions in the substrate manufacturing line. The computer program allows manufacturing to make cost-related decisions for several processing alternatives: send-aheads, recycles, reworks, and scrap. The model ensures the lowest to-stock cost processing based on the following variables: unit hours, yields, product flow, materials, and operating expenses. The use of this strategy and methodology results in reduced product cost, shorter cycle times, highlighting of process problems, and increased CFM (continuous flow manufacturing) efficiency. This approach could be incorporated in an expert system for a business modeling procedure meeting internal manufacturing and customer requirements View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The Leaders for Manufacturing Program: a new type of industry/university consortium

    Page(s): 186 - 187
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB)  

    A description is given of the Leaders for Manufacturing Program, an innovative program being conducted jointly by the Massachusetts Institute of Technology's School of Management and School of Engineering. The program represents a partnership between MIT and eleven major US corporations. It includes a graduate, dual-degree master's program as well as a research program in manufacturing. The vision and mission of the program, some of the details of the academic and research agendas, and the structure and operation of the partnership between the two schools at MIT and the eleven industrial partners are described View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Cantilever beam micro-contacts in a multi-chip interconnection system

    Page(s): 239 - 245
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (728 KB)  

    In order to examine the use of a compliant cantilever beam structure as a contact scheme for a multichip interconnection system (MIS), multilayer (metals and SiO2) cantilever beams were fabricated utilizing standard IC processing technologies and micromachining of silicon. The mechanical behavior and electrical characteristics of the beams were investigated to establish their optimum dimensions for use in the MIS. The number of inputs/outputs which can be achieved by this structure is ~1000 per 1-cm2 chip site. Au-to-Au contact resistance measurements, as a function of applied force, were carried out employing the Nanoindenter. The contact resistance data and the results from calculations on the maximum deflection and resisting force of these beams suggest that, through proper design, it is possible to achieve simultaneously acceptable and stable resistance values (< ~0.32 Ω) for signal transmission and reasonable flexibilities of beams. Computer simulation results show that the parasitics associated with a typical beam structure are very small (L~20 pH, C~20 fF) compared to conventional packaging technologies View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Applications of artificial intelligence in factory management

    Page(s): 18 - 22
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (544 KB)  

    Aspects of introducing AI-based technology to the manufacturing and administrative tasks encountered on the factory floor are discussed. In particular, it is indicated that the AI program has to be linked to the factory management or control system that contains the relevant shop floor data; this is usually not a trivial task. When AI technology is introduced to a factory floor, it is perceived as new, even in a factory environment where the introduction of new processing equipment or procedures is routine. Nonroutine newness on a factory floor is received with skepticism. For illustrative purposes, scheduling is used as the main application example. Attention is given to three issues: (1) integrating the AI program with the conventional technology needed for scheduling a factory; (2) support and training for AI applications, software, and hardware in a production environment; and (3) getting over the hurdle of introducing change in a production environment and making AI acceptable to factory managers View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Kinetic interactions of copper, lead and tin on solder coated PC boards studied using X-ray diffraction

    Page(s): 294 - 299
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB)  

    X-ray diffraction has been used to monitor the growth and decay of the constituent phases existing in solder (60% Sn-40% Pb) coated Cu printed circuit boards. Samples were aged from 145°C to 175°C for times sufficient to allow the Cu3Sn intermetallic phase X-ray peak count rate to exceed that for the Cu6Sn5 phase. Activation energies have been determined for the growth of (1) Cu6Sn5 and Cu3Sn and (2) the dissolution of crystalline from the solder matrix. The data indicate that the activation energy for Cu6Sn5 growth is Sn concentration dependent and can be related to the Sn solubility in Pb. The activation energy for Sn dissolution is not comparable to Sn lattice diffusion. A compressional d-space change in the Pb lattice induced by dissolved Sn is observed. The Pb(111) orientation is observed to grow preferentially during aging at all measured temperatures View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Using coarse/fine manipulation with vision to place fine pitch SMD components

    Page(s): 262 - 266
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (428 KB)  

    An experimental system that can accurately align and place SMDs (surface mount devices) on a printed circuit board is described. Features of the system are fine positioning and endpoint sensing after an IBM 7576 robot coarsely aligns the SMD to its target. Fine positioning is done using a customer-designed micropositioning device. The endpoint sensor is a single camera vision system that by image analysis determines the alignment error of the SMD to the board. System performance was evaluated by placing SMDs of 100 leads with 25 mil lead spacing on a board. The alignment error is less than 0.5 mil and 0.015°, independent of feeder and board position error or robot repeatability. The average cycle time is less than 10 s View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Dynamic behavior of SMT chip capacitors during solder reflow

    Page(s): 23 - 29
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    A dynamic model of a SMT (surface mount technology) type 1206 chip capacitor is developed. The model is used to determine the effects of pad geometry, chip metallization and dimensions, amount of solder, and chip displacement on the ability of the chip to lift (tombstone) and to self-align itself during solder reflow. Both static and dynamic characterizations are shown. The model simulations show that the chip capacitor will begin to lift initially for some geometries, but tombstoning does not appear to be a problem. Thus, to help the self-alignment capabilities, the simulations show that system configurations with smaller pad lengths, smaller pad gaps, larger solder volume, and smaller metallization are best. These conclusions are confirmed when compared to existing recommendations based upon experimental tests. It is concluded that the model is a powerful tool that can be used to optimize these system parameters View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Teaching, research and service in manufacturing at NJIT

    Page(s): 188 - 202
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (948 KB)  

    Manufacturing and engineering education activities at the New Jersey Institute of Technology (NJIT) are described. The primary objective of these activities is to prepare students to meet the challenge of the development and effective utilization of integrated information-driven manufacturing systems. Thus, the core of the program curricula consists of courses dealing with problems and methods of manufacturing systems integration, augmented for most students by an interdisciplinary team project performed in collaboration with industry. Also addressed is the need to prepare students to deal with problems at the element and subsystem level. Tables listing course contents are presented View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analyzing the mechanical strength of SMT attached solder joints

    Page(s): 61 - 69
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (468 KB)  

    Analytic approaches to the pull strength and shear strength of SMT (surface mount technology) attached solder joints have been studied by mathematical models. The predicted pull/shear strength of leaded ceramic quad packages correlated with the experimentally measured data quite well. Lead/pad design is shown to have the most significant impact on the solder joint strength. The design rules for butt leaded and land patterns have been developed. The predictive models have been used for defining the design guidelines for selecting the optimum lead/pad configurations, the minimum solder volume, and the maximum component misalignment for fine pitch SMT assemblies. The SPC (statistical process control) limits established through destructive mechanical testing can be used as online monitors for checking the short-term reliability of solder joints. The short-term reliability data generated by conducting destructive mechanical testing are complementary to the long-term reliability test View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Enhanced high speed performance from HDI thin film multi-chip modules

    Page(s): 355 - 366
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (824 KB)  

    A novel packaging technology, ideal for CMOS multichip modules, is described. Thin-film metal and polymer dielectric are used to fabricate five metal-layer structures with 25-μm-wide traces and 11-μm-thick dielectric layers. Features on the top pad layer can be fabricated to match the chip pads, allowing for orthogonal wire bonding with no fanout. In a microstrip configuration, the typical capacitance is 3.5 pF/in with a time of flight of about 160 ps/in. The propagation velocity (or phase velocity) for a sinusoidal wave is about 54% of the speed of light in vacuum. Multichip modules have been fabricated for applications ranging from two to 35 ICs, plus associated capacitors and resistors. With these features, the interconnect related propagation delay due to the capacitive loading or time of flight is in most cases less than the switching time of the driver gates (normally 1 ns). Low inductance power and ground planes are used throughout the module with on-board decoupling capacitors. Wire bonds on a 6-mil substrate pitch can be made routinely. The 6-mil pitch consists of a 4-mil pad and a 2-mil spacing between pads. With this pitch and short conductor lengths, bonding parasitics less than 1.2 nH are possible. Simultaneous switching noise is drastically reduced over conventional single-chip packaging methods View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Using process dissection to achieve design for manufacturability for electronic assemblies

    Page(s): 126 - 128
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB)  

    A DFM (design for manufacturability) concept called PPM dissection that uses the assembly defect rates in p.p.m.'s from measurements of variables controllable in the design phase is described. The material presented is on a most basic level, i.e. without the extensive equations and algorithms that make it work. A simple example is presented View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Maglev microrobotics: an approach toward highly integrated small-scale manufacturing systems

    Page(s): 273 - 276
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    It is noted that current industrial robots are poorly suited to many of the payload, precision, and integration requirements of the semiconductor industry. A general mechanical technology, based on magnetically levitated microrobots, that may be better matched to semiconductor manufacturing needs is described. Magnetic levitation has favorable downward scaling laws and can be used to build multiple-degree-of-freedom drives capable of high speeds (15 to 25 moves/s) and high precision (1 μm or better) using small manipulators (0.5 cm). A major advantage of the magnetic designs that were studied theoretically and experimentally is that they allow the use of small-motion, multiple-degree-of-freedom precision devices for long-distance, one-degree-of-freedom transport. Preliminary experimental results indicate that these systems can be batch-fabricated using printed-circuit-board or other planar technologies. Other advantages of magnetic levitation technology include loose fabrication tolerances, robustness in adverse environments, and reduced particulate generation relative to conventional robots View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Knowledge based control of adhesive dispensing for surface mount device assembly

    Page(s): 267 - 272
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    The results to date of a project using knowledge-based control techniques to resolve the problems encountered in the dispensing of the very viscous adhesives used to secure mounted components to mixed technology circuit boards before wave soldering are given. The work has two major thrusts, the accommodation of process variability with a rule-based system that controls a manufacturing cell and the accommodation of material variability with a real-time rule-based process control system. Dispensing problems are caused by variations in the material and system properties with, for example, batch, temperature, and time. A dispensing cell has been integrated that is able to use a rule-based object-oriented control system to resolve these problems View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Electronic system packaging: the search for manufacturing the optimum in a sea of constraints

    Page(s): 149 - 164
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1068 KB)  

    The author details some of the constraints on electronic system design and manufacturing that affect system performance, reliability, materials selection, and the assembly of the product. The electronic constraints include chip crossing delay, fanout (number of receivers on a driven net), crosstalk (unwanted electromagnetic coupling between independent signal lines and power supplies), DC voltage drop, the number of simultaneously switched line drivers, and reflections of signal waves from discontinuities in transmission line networks. The power dissipation constraints include materials, fabrication, and assembly. Some of the mathematical constraints are defined along with the coupling between them; optimum solutions are shown graphically. It is noted that the ability to resolve the system manufacturing constraints through optimization will determine the final success of a product View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Solderability test requirements for plastic surface mount packages

    Page(s): 30 - 37
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    The development of a filar eyepiece has increased the accuracy and repeatability of measurement of percent coverage after solderability testing. Using this refined dip-and-look or percent-coverage-after-dip method, the differences in hot solder coat and lead-tin solder plate solderability were evaluated. The plated coatings were shown to have better than 10% thickness uniformity across the lead surface. This is reflected in improved solderability after aging. With Sn/Pb plating, 90% coverage can be assured, as compared with the 80% coverage acceptance level for hot solder dip View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A successful strategy for implementing statistical process controls

    Page(s): 96 - 98
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB)  

    In the summer of 1987, the IBM Endicott (NY) Substrate Business Unit Management Team made a commitment to formulate and implement a comprehensive statistical process control (SPC) strategy for the entire substrate manufacturing line. The cornerstone of this strategy was the creation of a management support team consisting of upper-level management and statisticians to develop the strategy, manage the implementation, and resolve any problems. Process teams (one per unique process), consisting of a manufacturing engineer, quality engineer, statistician, and two key manufacturing operators, were then set up to study the process flow and its parameters to determine if control charts were appropriate. The implementation strategy is described. The accomplishments include: 177 control charts on the manufacturing floor, 23 technical reports that were written with 60 first-time authors, elimination of major sampling inspection gates, and control charts that continue to prevent major problems from occurring View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High performance controlled impedance interconnection system

    Page(s): 118 - 120
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB)  

    The limitation of future system performance of very high-speed, massively parallel computers and signal processors lies in the arena of electronic interconnections and packaging. Unless good solutions are found, systems will not be able to capitalize on the intrinsic capabilities of the latest active devices, which are capable of switching in the picosecond and even femtosecond domain. An interconnection system has been developed which permits the mating of 900 contacts per daughterboard to a motherboard. The unit is modular, so that a larger number (i.e. in excess of 20) daughterboards could be mated to a motherboard. Although the present design incorporates 900 contacts per daughterboard, this could be increased to 2000 contacts. All of the contacts have been designed with controlled impedance to 50 Ω. Units have been built, tested, and delivered to customers for their evaluation View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • In-line statistical process control and feedback for VLSI integrated circuit manufacturing

    Page(s): 70 - 75
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (512 KB)  

    A number of quality control and yield improvement techniques are used in the Hewlett Packard Fort Collins IC wafer fabrication line. Four of these are described, with examples of how each has improved quality and yield. Silicon wafer measurements obtained from the vendor or made at incoming inspection are correlated with device parameters and chip yield. Control charts on the manufacturing line are generated online from monitor wafer data entered by operators, giving immediate feedback. In addition, a daily summary report lists any chart out of control. In certain instances it is necessary to improve the process capability of an operation. A feedback technique is used to do this for operations which have predictable systematic drift. Individual wafer positions in critical operations are automatically recorded through the fabrication line. This greatly facilitates correlation of input to output parameters and pinpoints the root cause of physical, device parameter, or chip yield fluctuations. Rapid correlation of the data obtained throughout the fabrication and wafer test areas is done with a common database and tools which transform the raw data into an optimum form for analysis View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Is design realization a process? A case study

    Page(s): 344 - 354
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (636 KB)  

    A Bell Labs study of high-technology development and manufacturing activities has established that design realization is a process in a design organization. Process quality management and improvement methods were applied to the analysis, and an action plan was developed to improve the process. The analysis of the process indicated that a substantial fraction of the design cycle time is for noncreative activities such as waiting for models, duplication of effort, unanticipated delays in the delivery of custom piece parts, and redesigns to unstable design requirements. The impact of these delays is to increase the time from product conception to the time the product is available to the customers. Corrective actions have been proposed that include improvements in schedule tracking by management, developing and meeting milestones, planning, the front-end analysis of the design project for marketing and technical feasibility, the formation of an interdisciplinary team to carry the design from conception through manufacturing, and an education program. It has been proposed that the effectiveness of the recommendations be verified by applying them to current design projects View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Electron beam direct writing technology for printed wiring board

    Page(s): 246 - 250
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB)  

    An electron-beam lithography system has been developed which can write electric circuit patterns directly on printed wiring boards from computer-aided design data without making the master and working film masks which are necessary for conventional photolithography. The electron beam is focused to 34 μm in diameter at an accelerating voltage of 60 kV. The sensitivity of an electrodeposited photoresist to electron-beam exposure is investigated. It is shown that the photoresist is very sensitive to the electron beam and has a threshold dosage of 0.2 μC/cm2. The spatial contours of equienergy density deposited by the electron beam in a 20-μm-thick resist-copper substrate configuration have been calculated with a Monte Carlo computer method. The geometry of the resist patterns is determined according to the contour line corresponding to about 6×1018 eV/cm 3. It has been confirmed that fine patterns with linewidths less than 100 μm can be obtained and that this technology is efficient for meeting the constantly growing demand for greater density and shorter turnaround View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.