Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools

4-6 Sept. 2002

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  • Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools

    Publication Year: 2002
    Request permission for commercial reuse | PDF file iconPDF (368 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 2002, Page(s):393 - 394
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    Freely Available from IEEE
  • Evolutionary algorithm for state assignment of finite state machines

    Publication Year: 2002, Page(s):359 - 362
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (339 KB) | HTML iconHTML

    The paper proposes an evolutionary algorithm (EA) for the state assignment problem (SAP). Two original crossover operators are presented. They are experimentally compared with other known crossovers for SAP using a set of benchmark finite state machines. Solutions generated by EA (using different crossover operators) are compared with the random ones and with the state assignments generated by the... View full abstract»

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  • Hardware implementation of a memory allocator

    Publication Year: 2002, Page(s):355 - 358
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (330 KB) | HTML iconHTML

    It is generally felt that the complexity of system-on-chip (SOC) can only be addressed by intellectual-property (IP) based design. While IPs such as processor cores, memories, and bus controllers are being offered by many vendors, IP cores for dynamic memory management, an important task for any complex application, have been close to non-existent. This paper describes the implementation of a budd... View full abstract»

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  • Low power strategy for a TFT controller

    Publication Year: 2002, Page(s):351 - 354
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (430 KB) | HTML iconHTML

    In this paper a low power strategy for a TFT controller is described. The design is based on a general controller for high resolutions graphic display data. The main improvements introduced concerns not only an effective power reduction of about 65.42%, compared with the original module, but also the new feature that allows one to choose among six different functional configurations. The new TFT c... View full abstract»

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  • Analysis of the impact of different methods for division/square root computation in the performance of a superscalar microprocessor

    Publication Year: 2002, Page(s):218 - 225
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB) | HTML iconHTML

    An analysis of the impact of different methods for the double-precision computation of division and square root in the performance of a superscalar processor is presented in this paper. This analysis is carried out combining the SimpleScalar toolset, estimates of the latency and throughput of the compared methods and a set of benchmarks with typical features of intensive computing applications. Si... View full abstract»

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  • A self-timed arithmetic unit for elliptic curve cryptography

    Publication Year: 2002, Page(s):347 - 350
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (355 KB) | HTML iconHTML

    This paper describes an efficient implementation of a crypto arithmetic unit, which computes the modular-operations of addition, multiplication, and inversion in prime fields. These calculations are important for an application in elliptic curve cryptography (ECC). The hardware is designed in a self-timed and low-power approach. The paper discusses the pros and cons of this approach compared to a ... View full abstract»

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  • A design for a low-power digital matched filter applicable to W-CDMA

    Publication Year: 2002, Page(s):210 - 217
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1548 KB) | HTML iconHTML

    This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum (DS-SS) communication system. The proposed architectural approach to reducing the power consumption focuses on the reception registers and the correlation-calculating unit (CCU), which dissipate the majority of the power... View full abstract»

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  • Simplifying instruction issue logic in superscalar processors

    Publication Year: 2002, Page(s):341 - 346
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (377 KB) | HTML iconHTML

    Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instruction scheduling capability. However, it is difficult to increase the size without any serious impact on processor performance, since the instruction window is one of the dominant determiners of processor cycle time. The... View full abstract»

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  • Embedded software: how to make it efficient?

    Publication Year: 2002, Page(s):201 - 207
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (354 KB) | HTML iconHTML

    This paper stresses the importance of designing efficient embedded software and it provides a global view of some of the techniques that have been developed to meet this goal. These techniques include high-level transformations, compiler optimizations reducing the energy consumption of embedded programs and optimizations exploiting architectural features of embedded processors. Such optimizations ... View full abstract»

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  • Reachability analysis for formal verification of SystemC

    Publication Year: 2002, Page(s):337 - 340
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB) | HTML iconHTML

    With ever increasing design sizes, verification becomes the bottleneck in modem design flows. Up to 80% of the overall costs are due to the verification task. Formal methods have been proposed to overcome the limitations of simulation approaches. But these techniques have mainly been applied to lower levels of abstraction. With more and more design complexity the need for hardware description lang... View full abstract»

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  • Synthesis of multipurpose reversible logic gates

    Publication Year: 2002, Page(s):259 - 266
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1142 KB) | HTML iconHTML

    Regular reversible logic circuits, i.e. consisting of identical reversible gates, each of which is uniformly connected to its neighbors, have small garbage. Reversible gates realizing simultaneously some useful functions are very effective in synthesis of regular reversible logic circuits. In the paper we show how to create multipurpose reversible gates. Examples of efficient binary multipurpose r... View full abstract»

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  • Rapid prototyping of mixed hardware and software systems

    Publication Year: 2002, Page(s):118 - 125
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (573 KB) | HTML iconHTML

    This paper presents a practical approach to hardware/software partitioning, which is targeted at the rapid prototyping of embedded systems as a mixture of software and reconfigurable hardware. In our method, an application is firstly specified in the high-level programming language C - this is considered to be an executable functional specification. We subsequently allow this specification to be p... View full abstract»

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  • Improving mW/MHz ratio in FPGAs pipelined designs

    Publication Year: 2002, Page(s):276 - 282
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB) | HTML iconHTML

    This paper presents a simple clocking technique to migrate classical synchronous pipelined designs to a synchronous functional-equivalent alternative system in the context of FPGAs. When the new pipelined design runs at the same throughput of the original design, around 30% better mW/MHz ratio was observed in Virtex-based FPGA circuits. The evaluation is done using a simple but representative and ... View full abstract»

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  • Architecture design of a scalable single-chip multi-processor

    Publication Year: 2002, Page(s):132 - 139
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (462 KB) | HTML iconHTML

    Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is however the complexity of their interconnect and memory architecture. An example of a single-chip multi-processor for real-time (embedded) systems is the Multi Micro Processor (MμP). Its architecture consists of a scalable number of identical master proc... View full abstract»

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  • Improving the operation autonomy of SIMD processing elements by using guarded instructions and pseudo branches

    Publication Year: 2002, Page(s):148 - 155
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (469 KB) | HTML iconHTML

    This paper presents a novel method for improving the operation autonomy of the processing elements (PE) of SIMD-like machines. By combining guarded instructions and pseudo branches it is possible to achieve higher operation autonomy and higher instruction level parallelism than in previous SIMD/ASIMD architectures. The paper shows that it is feasible to avoid most branches and it is also possible ... View full abstract»

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  • Testability improvements based on the combination of analytical and evolutionary approaches at RT level

    Publication Year: 2002, Page(s):166 - 173
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (442 KB) | HTML iconHTML

    In the paper a new heuristic approach to the RTL testability analysis is presented It is shown how the values of controllability/observability factors reflecting the structure of the circuit and other factors can be utilised to find solutions which are sub-optimal but still acceptable for the designer. The goal of the methodology is to enable the identification of such testability solutions which ... View full abstract»

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  • Using formal tools to study complex circuits behaviour

    Publication Year: 2002, Page(s):180 - 186
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (366 KB) | HTML iconHTML

    We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential circuits described by flip-flops and gates. These complete and optimized representations help the designer to understand the accurate behaviour of the circuit. This deep understanding is a prerequisite for any verification or test process. An example is fully presented ... View full abstract»

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  • Networks on silicon: blessing or nightmare?

    Publication Year: 2002, Page(s):196 - 200
    Cited by:  Papers (25)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (772 KB) | HTML iconHTML

    Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those problems are encountered particularly on long wires for global interconnect. As clock frequencies increase, scaled wires become relatively slower and on-chip communication will be the limiting performance factor of future... View full abstract»

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  • Work out of the algorithm based on A-mod for detection of borderlines in images provided by the intravascular ultrasound system (IVUS) with 64 transducers

    Publication Year: 2002, Page(s):332 - 336
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (521 KB) | HTML iconHTML

    This paper presents algorithm based on A-mod of ultrasound signal for detection of borderlines and parameters of pictures for automated diagnostic, in pictures provided by the intravascular ultrasound system (IVUS) with 64 transducers. The subject of consideration was acoustic characteristics of blood and wall of blood vessel for propagation of ultrasound waves for solving the existing problem. Al... View full abstract»

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  • A hybrid evolutionary algorithm for Multi-FPGA systems design

    Publication Year: 2002, Page(s):60 - 67
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (832 KB) | HTML iconHTML

    Genetic algorithms (GAs) are stochastic optimization heuristics in which searches in solution space are carried out by imitating the population genetics stated in Darwin's theory of evolution. The compact genetic algorithm (cGA) does not manage a population of solutions but only mimics its existence. The combination of genetic and local search heuristic has been shown to be an effective approach t... View full abstract»

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  • Optimization of equational specifications using genetic techniques

    Publication Year: 2002, Page(s):252 - 258
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (383 KB) | HTML iconHTML

    One of the goals of a high level synthesis process is to minimize the circuit implementation cost. Since the minimization problem associated with those transformations is NP complete, in this work we present an evolutionary algorithm that optimize circuit specifications by means of a special type of genetic operator. We have named this operator algebraic mutation, carried out with the help of alge... View full abstract»

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  • An efficient list-based scheduling algorithm for high-level synthesis

    Publication Year: 2002, Page(s):316 - 323
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (495 KB) | HTML iconHTML

    Scheduling is considered as the most important task in high-level synthesis process. This paper presents a novel list-based scheduling algorithm based on incorporating some information extracted from data flow graph (DFG) structure to guide the scheduler to find near-optimal/optimal schedules quickly. We have developed a novel approach based on DFG analysis that is totally done as preparation phas... View full abstract»

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  • Specification and simulation of microprocessor operations and parallel instructions

    Publication Year: 2002, Page(s):110 - 117
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (470 KB) | HTML iconHTML

    In this paper we report on the development of a language which is especially tailored to the specification and simulation of microprocessor operations and parallel instructions. The approach is rigorous, and it combines the naturalness and readability of the traditional pseudocode with the formality and rigour of instruction specifications in the programming language C (but without the disadvantag... View full abstract»

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  • Folded bit-plane FIR filter architecture with changeable folding factor

    Publication Year: 2002, Page(s):45 - 52
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (993 KB) | HTML iconHTML

    The application of folding technique to the bit-plane systolic FIR filter architecture that enables the implementation of changeable folding factor onto the fixed size array is described in this paper. The transformation of original data flow graph (DFG) for bit-plane architecture that provides the successful application of the folding technique with changeable folding sets is presented. The invol... View full abstract»

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