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Digital System Design, 2002. Proceedings. Euromicro Symposium on

Date 4-6 Sept. 2002

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Displaying Results 1 - 25 of 55
  • Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools

    Publication Year: 2002
    Save to Project icon | Request Permissions | PDF file iconPDF (368 KB)  
    Freely Available from IEEE
  • Author index

    Publication Year: 2002 , Page(s): 393 - 394
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    Freely Available from IEEE
  • Integration of instruction set simulators into SystemC high level models

    Publication Year: 2002 , Page(s): 126 - 129
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (347 KB) |  | HTML iconHTML  

    This paper discusses the integration of instruction set simulators (ISS) for processor cores into highlevel system models. The approaches to providing data communication between high level modules and ISS are addressed as well as the synchronization between these parts. View full abstract»

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  • An efficient list-based scheduling algorithm for high-level synthesis

    Publication Year: 2002 , Page(s): 316 - 323
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (495 KB) |  | HTML iconHTML  

    Scheduling is considered as the most important task in high-level synthesis process. This paper presents a novel list-based scheduling algorithm based on incorporating some information extracted from data flow graph (DFG) structure to guide the scheduler to find near-optimal/optimal schedules quickly. We have developed a novel approach based on DFG analysis that is totally done as preparation phas... View full abstract»

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  • Optimization of equational specifications using genetic techniques

    Publication Year: 2002 , Page(s): 252 - 258
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (383 KB) |  | HTML iconHTML  

    One of the goals of a high level synthesis process is to minimize the circuit implementation cost. Since the minimization problem associated with those transformations is NP complete, in this work we present an evolutionary algorithm that optimize circuit specifications by means of a special type of genetic operator. We have named this operator algebraic mutation, carried out with the help of alge... View full abstract»

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  • Work out of the algorithm based on A-mod for detection of borderlines in images provided by the intravascular ultrasound system (IVUS) with 64 transducers

    Publication Year: 2002 , Page(s): 332 - 336
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (521 KB) |  | HTML iconHTML  

    This paper presents algorithm based on A-mod of ultrasound signal for detection of borderlines and parameters of pictures for automated diagnostic, in pictures provided by the intravascular ultrasound system (IVUS) with 64 transducers. The subject of consideration was acoustic characteristics of blood and wall of blood vessel for propagation of ultrasound waves for solving the existing problem. Al... View full abstract»

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  • Simplifying instruction issue logic in superscalar processors

    Publication Year: 2002 , Page(s): 341 - 346
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (377 KB) |  | HTML iconHTML  

    Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instruction scheduling capability. However, it is difficult to increase the size without any serious impact on processor performance, since the instruction window is one of the dominant determiners of processor cycle time. The... View full abstract»

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  • Systems are made from transistors: UDSM technology creates new challenges for library and IC development

    Publication Year: 2002
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1337 KB) |  | HTML iconHTML  

    The progress of silicon process technology relentlessly marches on. Moore's law still holds, the number of transistors that can be integrated on an IC doubles approximately every 18 months. The inability of system designs to keep up with this ever increasing number of available transistors has been debated for a long time, many solutions have been proposed. Now, as 130 nm processes enter volume pr... View full abstract»

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  • Improving mW/MHz ratio in FPGAs pipelined designs

    Publication Year: 2002 , Page(s): 276 - 282
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (356 KB) |  | HTML iconHTML  

    This paper presents a simple clocking technique to migrate classical synchronous pipelined designs to a synchronous functional-equivalent alternative system in the context of FPGAs. When the new pipelined design runs at the same throughput of the original design, around 30% better mW/MHz ratio was observed in Virtex-based FPGA circuits. The evaluation is done using a simple but representative and ... View full abstract»

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  • A self-timed arithmetic unit for elliptic curve cryptography

    Publication Year: 2002 , Page(s): 347 - 350
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (355 KB) |  | HTML iconHTML  

    This paper describes an efficient implementation of a crypto arithmetic unit, which computes the modular-operations of addition, multiplication, and inversion in prime fields. These calculations are important for an application in elliptic curve cryptography (ECC). The hardware is designed in a self-timed and low-power approach. The paper discusses the pros and cons of this approach compared to a ... View full abstract»

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  • Networks on silicon: blessing or nightmare?

    Publication Year: 2002 , Page(s): 196 - 200
    Cited by:  Papers (19)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (772 KB) |  | HTML iconHTML  

    Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those problems are encountered particularly on long wires for global interconnect. As clock frequencies increase, scaled wires become relatively slower and on-chip communication will be the limiting performance factor of future... View full abstract»

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  • Reachability analysis for formal verification of SystemC

    Publication Year: 2002 , Page(s): 337 - 340
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (372 KB) |  | HTML iconHTML  

    With ever increasing design sizes, verification becomes the bottleneck in modem design flows. Up to 80% of the overall costs are due to the verification task. Formal methods have been proposed to overcome the limitations of simulation approaches. But these techniques have mainly been applied to lower levels of abstraction. With more and more design complexity the need for hardware description lang... View full abstract»

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  • Use of the autocorrelation function in the classification of switching functions

    Publication Year: 2002 , Page(s): 244 - 251
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (398 KB) |  | HTML iconHTML  

    Four operations on switching functions are used to define a classification technique based on the autocorrelation function. The relationship between these classes and the well-known spectral classes is investigated, and a canonical representative for each class is proposed. It is thought that these classes will be of use in logic synthesis employing decision diagram representations for intermediat... View full abstract»

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  • Embedded software: how to make it efficient?

    Publication Year: 2002 , Page(s): 201 - 207
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (354 KB) |  | HTML iconHTML  

    This paper stresses the importance of designing efficient embedded software and it provides a global view of some of the techniques that have been developed to meet this goal. These techniques include high-level transformations, compiler optimizations reducing the energy consumption of embedded programs and optimizations exploiting architectural features of embedded processors. Such optimizations ... View full abstract»

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  • Architecture design of a scalable single-chip multi-processor

    Publication Year: 2002 , Page(s): 132 - 139
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (462 KB) |  | HTML iconHTML  

    Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is however the complexity of their interconnect and memory architecture. An example of a single-chip multi-processor for real-time (embedded) systems is the Multi Micro Processor (MμP). Its architecture consists of a scalable number of identical master proc... View full abstract»

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  • Enhanced reusability for SoC-based HW/SW co-design

    Publication Year: 2002 , Page(s): 94 - 99
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (305 KB) |  | HTML iconHTML  

    This paper addresses design methods for SoC-based HW/SW systems using reconfigurable architectures. The emphasis is the development of a method to enhance the reusability of HW and SW in the co-design process using proven languages like ANSI-C and VHDL. We distinguish between three abstraction layers for design modules consisting of both HW and SW This approach benefits the reuse of HW sources as ... View full abstract»

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  • Parallel multimedia processor using customised Infineon TriCores

    Publication Year: 2002 , Page(s): 140 - 147
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (347 KB) |  | HTML iconHTML  

    This paper reports on our experiments on using the Infineon TriCore as a building block for a multimedia processor. The experiments aim to obtain a high performance processor using two strategies: integrating multimedia units into the TriCore CPU and constructing the TriCore in multiprocessor configuration. The design and implementation of the multimedia units for video, audio, and text compressio... View full abstract»

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  • Recursive bi-partitioning of netlists for large number of partitions

    Publication Year: 2002 , Page(s): 38 - 44
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (369 KB) |  | HTML iconHTML  

    In many application in VLSI CAD, a given netlist has to be partitioned into smaller sub-designs which can be handled much better. In this paper we present a new recursive bi-partitioning algorithm that is especially applicable, if a large number of final partitions, e.g. more than 1000, has to be computed. The algorithm consists of two steps. Based on recursive splits the problem is divided into s... View full abstract»

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  • The synthesis of a hardware scheduler for non-manifest loops

    Publication Year: 2002 , Page(s): 78 - 85
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (479 KB) |  | HTML iconHTML  

    This paper addresses the hardware implementation of a dynamic scheduler for non-manifest data dependent periodic loops. Static scheduling techniques which are known to give near optimal scheduling-solutions for manifest loops, fail at scheduling non-manifest loops, since they lack the run time information needed which makes a static schedule feasible. In this paper a dynamic scheduling approach wa... View full abstract»

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  • Improving the operation autonomy of SIMD processing elements by using guarded instructions and pseudo branches

    Publication Year: 2002 , Page(s): 148 - 155
    Cited by:  Papers (7)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (469 KB) |  | HTML iconHTML  

    This paper presents a novel method for improving the operation autonomy of the processing elements (PE) of SIMD-like machines. By combining guarded instructions and pseudo branches it is possible to achieve higher operation autonomy and higher instruction level parallelism than in previous SIMD/ASIMD architectures. The paper shows that it is feasible to avoid most branches and it is also possible ... View full abstract»

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  • Evolutionary algorithm for state assignment of finite state machines

    Publication Year: 2002 , Page(s): 359 - 362
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (339 KB) |  | HTML iconHTML  

    The paper proposes an evolutionary algorithm (EA) for the state assignment problem (SAP). Two original crossover operators are presented. They are experimentally compared with other known crossovers for SAP using a set of benchmark finite state machines. Solutions generated by EA (using different crossover operators) are compared with the random ones and with the state assignments generated by the... View full abstract»

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  • Formal verification of a DSP chip using an iterative approach

    Publication Year: 2002 , Page(s): 12 - 19
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (403 KB) |  | HTML iconHTML  

    In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and structural descriptions of the processor. Our methodology consists of first simplifying the representations of the DSP units. We then prove for each unit that its hardware description implies its behavioral specification. Usi... View full abstract»

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  • Synthesis of multipurpose reversible logic gates

    Publication Year: 2002 , Page(s): 259 - 266
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1142 KB) |  | HTML iconHTML  

    Regular reversible logic circuits, i.e. consisting of identical reversible gates, each of which is uniformly connected to its neighbors, have small garbage. Reversible gates realizing simultaneously some useful functions are very effective in synthesis of regular reversible logic circuits. In the paper we show how to create multipurpose reversible gates. Examples of efficient binary multipurpose r... View full abstract»

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  • Enhanced configurable parallel memory architecture

    Publication Year: 2002 , Page(s): 28 - 35
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1173 KB) |  | HTML iconHTML  

    Contemporary multimedia processors and applications are increasingly limited by their data accessing capabilities. However, the designed Configurable Parallel Memory Architecture (CPMA) alleviates these multimedia data accessing requirements; achieving significant performance improvements over traditional memory architectures. CPMA decreases considerably the processor-memory bottleneck by widening... View full abstract»

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  • On the fundamental design gap in terabit per second packet switching

    Publication Year: 2002 , Page(s): 371 - 378
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (329 KB) |  | HTML iconHTML  

    We discuss the gap we experience in an industrial design path of high-speed packet switches. As bandwidth demand exceeds progress in CMOS technology, system architects are forced to abandon familiar design solutions and make fundamental changes to their architectures at an increasingly faster pace. We investigate design methods to decrease the risk of such changes and to provide a structured and c... View full abstract»

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