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Digital System Design, 2002. Proceedings. Euromicro Symposium on

Date 4-6 Sept. 2002

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Displaying Results 1 - 25 of 55
  • Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools

    Publication Year: 2002
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    Freely Available from IEEE
  • Author index

    Publication Year: 2002, Page(s):393 - 394
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    Freely Available from IEEE
  • Work out of the algorithm based on A-mod for detection of borderlines in images provided by the intravascular ultrasound system (IVUS) with 64 transducers

    Publication Year: 2002, Page(s):332 - 336
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (521 KB) | HTML iconHTML

    This paper presents algorithm based on A-mod of ultrasound signal for detection of borderlines and parameters of pictures for automated diagnostic, in pictures provided by the intravascular ultrasound system (IVUS) with 64 transducers. The subject of consideration was acoustic characteristics of blood and wall of blood vessel for propagation of ultrasound waves for solving the existing problem. Al... View full abstract»

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  • On the fundamental design gap in terabit per second packet switching

    Publication Year: 2002, Page(s):371 - 378
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (329 KB) | HTML iconHTML

    We discuss the gap we experience in an industrial design path of high-speed packet switches. As bandwidth demand exceeds progress in CMOS technology, system architects are forced to abandon familiar design solutions and make fundamental changes to their architectures at an increasingly faster pace. We investigate design methods to decrease the risk of such changes and to provide a structured and c... View full abstract»

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  • Source code transformation to improve conditional hardware reuse

    Publication Year: 2002, Page(s):324 - 330
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1006 KB) | HTML iconHTML

    The computations of a system whose behavior varies depending on the value of some conditions may present a property called mutual exclusiveness. This property, responsible for the degree of conditional reuse achievable after a high-level synthesis (HLS) process, is intrinsic to the behavior. But sometimes it is only partially reflected in the actual description written by a designer, leading to wo... View full abstract»

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  • Use of HDL code checkers to support the IP entrance check - a requirement analysis

    Publication Year: 2002, Page(s):364 - 370
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB) | HTML iconHTML

    Systems for coding style analysis, so called hardware description languages (HDL) code checkers, can accomplish an important contribution for the IP entrance check, that means selection, compliance test and quality estimation of reusable components for the system design. This paper summarizes the related requirements on HDL code checkers derived from a concrete industrial environment. A proposed e... View full abstract»

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  • Parallel multimedia processor using customised Infineon TriCores

    Publication Year: 2002, Page(s):140 - 147
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (347 KB) | HTML iconHTML

    This paper reports on our experiments on using the Infineon TriCore as a building block for a multimedia processor. The experiments aim to obtain a high performance processor using two strategies: integrating multimedia units into the TriCore CPU and constructing the TriCore in multiprocessor configuration. The design and implementation of the multimedia units for video, audio, and text compressio... View full abstract»

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  • Configurable memory organisation for communication applications

    Publication Year: 2002, Page(s):86 - 93
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1677 KB) | HTML iconHTML

    A configurable memory organisation for the execution of Hiperlan/2 transceiver baseband processing and MPEG2 decoding is presented. The configuration of the memory system is done by controlling the DSP processor's access to memory buses with an external processor and switches. The configurable memory organisation allows the scaling of system capacity to the needs of the applications and makes the ... View full abstract»

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  • A design for a low-power digital matched filter applicable to W-CDMA

    Publication Year: 2002, Page(s):210 - 217
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1548 KB) | HTML iconHTML

    This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum (DS-SS) communication system. The proposed architectural approach to reducing the power consumption focuses on the reception registers and the correlation-calculating unit (CCU), which dissipate the majority of the power... View full abstract»

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  • An efficient list-based scheduling algorithm for high-level synthesis

    Publication Year: 2002, Page(s):316 - 323
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (495 KB) | HTML iconHTML

    Scheduling is considered as the most important task in high-level synthesis process. This paper presents a novel list-based scheduling algorithm based on incorporating some information extracted from data flow graph (DFG) structure to guide the scheduler to find near-optimal/optimal schedules quickly. We have developed a novel approach based on DFG analysis that is totally done as preparation phas... View full abstract»

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  • Evolutionary algorithm for state assignment of finite state machines

    Publication Year: 2002, Page(s):359 - 362
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (339 KB) | HTML iconHTML

    The paper proposes an evolutionary algorithm (EA) for the state assignment problem (SAP). Two original crossover operators are presented. They are experimentally compared with other known crossovers for SAP using a set of benchmark finite state machines. Solutions generated by EA (using different crossover operators) are compared with the random ones and with the state assignments generated by the... View full abstract»

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  • Architecture design of a scalable single-chip multi-processor

    Publication Year: 2002, Page(s):132 - 139
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (462 KB) | HTML iconHTML

    Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is however the complexity of their interconnect and memory architecture. An example of a single-chip multi-processor for real-time (embedded) systems is the Multi Micro Processor (MμP). Its architecture consists of a scalable number of identical master proc... View full abstract»

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  • A hybrid evolutionary algorithm for Multi-FPGA systems design

    Publication Year: 2002, Page(s):60 - 67
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (832 KB) | HTML iconHTML

    Genetic algorithms (GAs) are stochastic optimization heuristics in which searches in solution space are carried out by imitating the population genetics stated in Darwin's theory of evolution. The compact genetic algorithm (cGA) does not manage a population of solutions but only mimics its existence. The combination of genetic and local search heuristic has been shown to be an effective approach t... View full abstract»

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  • Simplifying instruction issue logic in superscalar processors

    Publication Year: 2002, Page(s):341 - 346
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (377 KB) | HTML iconHTML

    Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instruction scheduling capability. However, it is difficult to increase the size without any serious impact on processor performance, since the instruction window is one of the dominant determiners of processor cycle time. The... View full abstract»

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  • Bit-level allocation of multiple-precision specifications

    Publication Year: 2002, Page(s):385 - 392
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (462 KB) | HTML iconHTML

    This paper proposes an allocation algorithm able to perform the combined resource selection and operation binding of multiple-precision specifications that maximizes the bit-level reuse of hardware resources. Additionally, it presents an analytic method to estimate the amount of area that our approach could save in comparison with traditional allocation algorithms. In order to minimize the cost of... View full abstract»

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  • Implementation of a streaming execution unit

    Publication Year: 2002, Page(s):156 - 164
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (441 KB) | HTML iconHTML

    The Complex Streamed Instruction (CSI) set is an ISA extension targeted at multimedia applications. CSI instructions process two-dimensional data streams stored in memory, performing sectioning, data alignment and conversion between different packed data types all in hardware. It has been shown previously that CSI provides significant speedups compared to current media ISA extensions such as MMX a... View full abstract»

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  • The synthesis of a hardware scheduler for non-manifest loops

    Publication Year: 2002, Page(s):78 - 85
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (479 KB) | HTML iconHTML

    This paper addresses the hardware implementation of a dynamic scheduler for non-manifest data dependent periodic loops. Static scheduling techniques which are known to give near optimal scheduling-solutions for manifest loops, fail at scheduling non-manifest loops, since they lack the run time information needed which makes a static schedule feasible. In this paper a dynamic scheduling approach wa... View full abstract»

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  • Fault latencies of concurrent checking FSMs

    Publication Year: 2002, Page(s):174 - 179
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB) | HTML iconHTML

    In this paper we introduce concepts of a potential fault latency and a real fault latency for Finite State Machines (FSMs). The potential latency defines a minimal value of the possible latency for an FSM, while the real latency relates to the certain implementation of the FSM A method for investigation of latencies for online checking FSMs is described This technique is based on selection of traj... View full abstract»

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  • Integrated design and test generation under internet based environment MOSCITO

    Publication Year: 2002, Page(s):187 - 194
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (481 KB) | HTML iconHTML

    This paper describes an environment for internet-based collaboration in the field of design and test of digital systems. Automatic Test Pattern Generation (ATPG) and fault simulation tools at behavioral, logical and hierarchical levels available at geographically different places running under the virtual environment using the MOSCITO system are presented The interfaces between the integrated tool... View full abstract»

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  • Embedded software: how to make it efficient?

    Publication Year: 2002, Page(s):201 - 207
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (354 KB) | HTML iconHTML

    This paper stresses the importance of designing efficient embedded software and it provides a global view of some of the techniques that have been developed to meet this goal. These techniques include high-level transformations, compiler optimizations reducing the energy consumption of embedded programs and optimizations exploiting architectural features of embedded processors. Such optimizations ... View full abstract»

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  • Performance of remote FPGA-based coprocessors for image-processing applications

    Publication Year: 2002, Page(s):268 - 275
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB) | HTML iconHTML

    This paper describes a performance evaluation of image-processing applications on FPGA-based coprocessors that are part of general-purpose computers. Our experiments show that the maximum speed-up depends on the amount of data processed by the coprocessor. Taking images with 256×256 pixels, a moderate FPGA capacity of 10E+5 CLBs provides two orders of magnitude of performance improvement ove... View full abstract»

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  • Optimization of equational specifications using genetic techniques

    Publication Year: 2002, Page(s):252 - 258
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (383 KB) | HTML iconHTML

    One of the goals of a high level synthesis process is to minimize the circuit implementation cost. Since the minimization problem associated with those transformations is NP complete, in this work we present an evolutionary algorithm that optimize circuit specifications by means of a special type of genetic operator. We have named this operator algebraic mutation, carried out with the help of alge... View full abstract»

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  • Efficient verification of scheduling, allocation and binding in high-level synthesis

    Publication Year: 2002, Page(s):308 - 315
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB) | HTML iconHTML

    This paper presents an efficient method to solve an important aspect of the high-level verification problem: the formal verification of RT-level implementations (datapath + controller), obtained from algorithmic-level specifications by high-level synthesis tools. The method consists in replicating external, and potentially incorrect, design processes within a mathematical framework, giving as a re... View full abstract»

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  • Decision diagram optimization using copy properties

    Publication Year: 2002, Page(s):236 - 243
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (458 KB) | HTML iconHTML

    In this paper, we propose an approach to the reduction of sizes of multi-terminal binary decision diagrams (MTBDDs) by using the copy properties of discrete functions. The underlying principles come from copy theory of discrete signals considered previously. We propose two modifications of MTBDDs, called copy DDs (CDDs) and half copy DDs (HCDDs), using the corresponding copy operations from copy t... View full abstract»

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  • Hardware implementation of a memory allocator

    Publication Year: 2002, Page(s):355 - 358
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (330 KB) | HTML iconHTML

    It is generally felt that the complexity of system-on-chip (SOC) can only be addressed by intellectual-property (IP) based design. While IPs such as processor cores, memories, and bus controllers are being offered by many vendors, IP cores for dynamic memory management, an important task for any complex application, have been close to non-existent. This paper describes the implementation of a budd... View full abstract»

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