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Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools

4-6 Sept. 2002

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  • Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools

    Publication Year: 2002
    Request permission for commercial reuse | PDF file iconPDF (368 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 2002, Page(s):393 - 394
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    Freely Available from IEEE
  • Use of HDL code checkers to support the IP entrance check - a requirement analysis

    Publication Year: 2002, Page(s):364 - 370
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB) | HTML iconHTML

    Systems for coding style analysis, so called hardware description languages (HDL) code checkers, can accomplish an important contribution for the IP entrance check, that means selection, compliance test and quality estimation of reusable components for the system design. This paper summarizes the related requirements on HDL code checkers derived from a concrete industrial environment. A proposed e... View full abstract»

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  • Evolutionary algorithm for state assignment of finite state machines

    Publication Year: 2002, Page(s):359 - 362
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (339 KB) | HTML iconHTML

    The paper proposes an evolutionary algorithm (EA) for the state assignment problem (SAP). Two original crossover operators are presented. They are experimentally compared with other known crossovers for SAP using a set of benchmark finite state machines. Solutions generated by EA (using different crossover operators) are compared with the random ones and with the state assignments generated by the... View full abstract»

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  • Hardware implementation of a memory allocator

    Publication Year: 2002, Page(s):355 - 358
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (330 KB) | HTML iconHTML

    It is generally felt that the complexity of system-on-chip (SOC) can only be addressed by intellectual-property (IP) based design. While IPs such as processor cores, memories, and bus controllers are being offered by many vendors, IP cores for dynamic memory management, an important task for any complex application, have been close to non-existent. This paper describes the implementation of a budd... View full abstract»

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  • Parallel multimedia processor using customised Infineon TriCores

    Publication Year: 2002, Page(s):140 - 147
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (347 KB) | HTML iconHTML

    This paper reports on our experiments on using the Infineon TriCore as a building block for a multimedia processor. The experiments aim to obtain a high performance processor using two strategies: integrating multimedia units into the TriCore CPU and constructing the TriCore in multiprocessor configuration. The design and implementation of the multimedia units for video, audio, and text compressio... View full abstract»

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  • Using formal tools to study complex circuits behaviour

    Publication Year: 2002, Page(s):180 - 186
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (366 KB) | HTML iconHTML

    We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential circuits described by flip-flops and gates. These complete and optimized representations help the designer to understand the accurate behaviour of the circuit. This deep understanding is a prerequisite for any verification or test process. An example is fully presented ... View full abstract»

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  • Reconfigurable hardware implementation of Montgomery modular multiplication and parallel binary exponentiation

    Publication Year: 2002, Page(s):226 - 233
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2956 KB) | HTML iconHTML

    Modular exponentiation and modular multiplication are the cornerstone computations performed in public-key cryptography systems such as RSA cryptosystem. The operations are time consuming for large operands. Much research effort is directed towards an efficient hardware implementation of both operations. This paper describes the characteristics of two architectures: the first one implements modula... View full abstract»

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  • Low power strategy for a TFT controller

    Publication Year: 2002, Page(s):351 - 354
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (430 KB) | HTML iconHTML

    In this paper a low power strategy for a TFT controller is described. The design is based on a general controller for high resolutions graphic display data. The main improvements introduced concerns not only an effective power reduction of about 65.42%, compared with the original module, but also the new feature that allows one to choose among six different functional configurations. The new TFT c... View full abstract»

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  • Architecture design of a scalable single-chip multi-processor

    Publication Year: 2002, Page(s):132 - 139
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (462 KB) | HTML iconHTML

    Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is however the complexity of their interconnect and memory architecture. An example of a single-chip multi-processor for real-time (embedded) systems is the Multi Micro Processor (MμP). Its architecture consists of a scalable number of identical master proc... View full abstract»

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  • Constant coefficient convolution implemented in FPGAs

    Publication Year: 2002, Page(s):291 - 298
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (430 KB) | HTML iconHTML

    This paper reviews different architectural solutions for calculating constant coefficient convolution operation in FPGAs. At first, different architectures of multipliers are approached, as the multiplication is the most complex operation performed in the convolutions. Nevertheless, disregarding the multiplier entity allows for further circuit optimisations. Therefore look-up-table (LUT) based con... View full abstract»

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  • Fault latencies of concurrent checking FSMs

    Publication Year: 2002, Page(s):174 - 179
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB) | HTML iconHTML

    In this paper we introduce concepts of a potential fault latency and a real fault latency for Finite State Machines (FSMs). The potential latency defines a minimal value of the possible latency for an FSM, while the real latency relates to the certain implementation of the FSM A method for investigation of latencies for online checking FSMs is described This technique is based on selection of traj... View full abstract»

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  • Analysis of the impact of different methods for division/square root computation in the performance of a superscalar microprocessor

    Publication Year: 2002, Page(s):218 - 225
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB) | HTML iconHTML

    An analysis of the impact of different methods for the double-precision computation of division and square root in the performance of a superscalar processor is presented in this paper. This analysis is carried out combining the SimpleScalar toolset, estimates of the latency and throughput of the compared methods and a set of benchmarks with typical features of intensive computing applications. Si... View full abstract»

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  • Performance of remote FPGA-based coprocessors for image-processing applications

    Publication Year: 2002, Page(s):268 - 275
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB) | HTML iconHTML

    This paper describes a performance evaluation of image-processing applications on FPGA-based coprocessors that are part of general-purpose computers. Our experiments show that the maximum speed-up depends on the amount of data processed by the coprocessor. Taking images with 256×256 pixels, a moderate FPGA capacity of 10E+5 CLBs provides two orders of magnitude of performance improvement ove... View full abstract»

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  • A self-timed arithmetic unit for elliptic curve cryptography

    Publication Year: 2002, Page(s):347 - 350
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (355 KB) | HTML iconHTML

    This paper describes an efficient implementation of a crypto arithmetic unit, which computes the modular-operations of addition, multiplication, and inversion in prime fields. These calculations are important for an application in elliptic curve cryptography (ECC). The hardware is designed in a self-timed and low-power approach. The paper discusses the pros and cons of this approach compared to a ... View full abstract»

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  • Integration of instruction set simulators into SystemC high level models

    Publication Year: 2002, Page(s):126 - 129
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (347 KB) | HTML iconHTML

    This paper discusses the integration of instruction set simulators (ISS) for processor cores into highlevel system models. The approaches to providing data communication between high level modules and ISS are addressed as well as the synchronization between these parts. View full abstract»

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  • Design of an FPGA based adaptive neural controller for intelligent robot navigation

    Publication Year: 2002, Page(s):283 - 290
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (969 KB) | HTML iconHTML

    This article describes an alternative hardware solution to be implemented on FPGAs (field programmable gate array) for collision free robot navigation. A RAM based artificial neural network (ANN) was considered as the heart of the controller due to the advantage of its ease of implementation in conventional hardware. The structure of the ANN was well suited to realize the experiments for evolution... View full abstract»

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  • Testability improvements based on the combination of analytical and evolutionary approaches at RT level

    Publication Year: 2002, Page(s):166 - 173
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (442 KB) | HTML iconHTML

    In the paper a new heuristic approach to the RTL testability analysis is presented It is shown how the values of controllability/observability factors reflecting the structure of the circuit and other factors can be utilised to find solutions which are sub-optimal but still acceptable for the designer. The goal of the methodology is to enable the identification of such testability solutions which ... View full abstract»

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  • An asynchronous victim cache

    Publication Year: 2002, Page(s):4 - 11
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (397 KB) | HTML iconHTML

    Memory bandwidth is a limiting factor with many modem microprocessors and it is usual to include a cache to reduce the amount of memory traffic. Of the two commonly used cache write-policies, the copy-back approach is better than the write-through approach in this respect. The performance of both approaches can be further aided by the inclusion of a small buffer in the path of outgoing writes to t... View full abstract»

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  • A design for a low-power digital matched filter applicable to W-CDMA

    Publication Year: 2002, Page(s):210 - 217
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1548 KB) | HTML iconHTML

    This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum (DS-SS) communication system. The proposed architectural approach to reducing the power consumption focuses on the reception registers and the correlation-calculating unit (CCU), which dissipate the majority of the power... View full abstract»

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  • Synthesis of multipurpose reversible logic gates

    Publication Year: 2002, Page(s):259 - 266
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1142 KB) | HTML iconHTML

    Regular reversible logic circuits, i.e. consisting of identical reversible gates, each of which is uniformly connected to its neighbors, have small garbage. Reversible gates realizing simultaneously some useful functions are very effective in synthesis of regular reversible logic circuits. In the paper we show how to create multipurpose reversible gates. Examples of efficient binary multipurpose r... View full abstract»

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  • Simplifying instruction issue logic in superscalar processors

    Publication Year: 2002, Page(s):341 - 346
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (377 KB) | HTML iconHTML

    Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instruction scheduling capability. However, it is difficult to increase the size without any serious impact on processor performance, since the instruction window is one of the dominant determiners of processor cycle time. The... View full abstract»

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  • Rapid prototyping of mixed hardware and software systems

    Publication Year: 2002, Page(s):118 - 125
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (573 KB) | HTML iconHTML

    This paper presents a practical approach to hardware/software partitioning, which is targeted at the rapid prototyping of embedded systems as a mixture of software and reconfigurable hardware. In our method, an application is firstly specified in the high-level programming language C - this is considered to be an executable functional specification. We subsequently allow this specification to be p... View full abstract»

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  • On the fundamental design gap in terabit per second packet switching

    Publication Year: 2002, Page(s):371 - 378
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (329 KB) | HTML iconHTML

    We discuss the gap we experience in an industrial design path of high-speed packet switches. As bandwidth demand exceeds progress in CMOS technology, system architects are forced to abandon familiar design solutions and make fundamental changes to their architectures at an increasingly faster pace. We investigate design methods to decrease the risk of such changes and to provide a structured and c... View full abstract»

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  • Improving the operation autonomy of SIMD processing elements by using guarded instructions and pseudo branches

    Publication Year: 2002, Page(s):148 - 155
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (469 KB) | HTML iconHTML

    This paper presents a novel method for improving the operation autonomy of the processing elements (PE) of SIMD-like machines. By combining guarded instructions and pseudo branches it is possible to achieve higher operation autonomy and higher instruction level parallelism than in previous SIMD/ASIMD architectures. The paper shows that it is feasible to avoid most branches and it is also possible ... View full abstract»

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