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Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International

Date 15-17 Feb. 1989

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Displaying Results 1 - 25 of 103
  • 1989 36th IEEE International Solid-State Circuits Conference - Digest of Technical Papers ISSCC [front matter]

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  • Table of contents

    Page(s): 4 - 10
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  • 1-volt operational amplifier with rail-to-rail input and output ranges

    Page(s): 64 - 65
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    A bipolar integrated operational amplifier (op amp), operating over nearly the full supply voltage range when the supply voltage is 1 V or more, has been designed with an input stage which can handle signals beyond the supply rails and an output stage which is able to operate within 10 mV of the supply rails. Characteristics of the op amp are 0.7-mV offset, 75-nV/ square root Hz noise, 450-kHz bandwidth, and 40-dB worst-case common-mode rejection ratio. The input and output stages are shown.<> View full abstract»

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  • A 10-bit video BiCMOS track-and-hold

    Page(s): 68 - 69
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    The authors describe a monolithic track-and-hold circuit with performance competitive with state-of-the art hybrid systems and surpassing that of previously reported monolithic implementations by nearly two orders of magnitude. The circuit has been integrated in an advanced BiCMOS technology. It operates from +or-5 V power supplies and is capable of driving a 50- Omega load with a voltage swing of +or-1 V. The circuit settles to an accuracy of 10 bits in less than 15 ns. The power consumption is 630 mW for a single-ended implementation and 1.2 W for a fully differential configuration. A block diagram of the differential system consisting of two identical track-and-hold circuits with a common switch driver is presented. The performance of the track-and-hold system is summarized.<> View full abstract»

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  • A wideband class-B video output driver

    Page(s): 70 - 71
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    The authors describe a high-resolution class-B video output driver IC for analog or digital video display systems. The IC, which uses a single 5-V supply, is combined with high-voltage discrete output power transistors to drive either a color or a monochrome CRT (cathode ray tube). The system yields greater bandwidth while consuming one third the power required by conventional class-A CRT drivers. The circuit was fabricated in a 2- mu m oxide-isolated bipolar process with peak f/sub T/ approximately=8 GHz. Using discrete output transistors (f/sub T/=1 GHz, C/sub CB/=2pF), board testing on a CRT with a nominal 10-pF load yielded approximately 15-ns output rise and fall times with 45-V swing and 60-mA slew current limit.<> View full abstract»

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  • A 10 GHz operational amplifier in GaAs MESFET technology

    Page(s): 72 - 73
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    Previous implementations of high-performance op amps in GaAs technology have been hindered by low transistor g/sub m/r/sub ds/, light sensitivity, and excessive backgating, which have limited gain and bandwidth. These limitations are overcome in the circuit reported here by the use of improved processing technologies and circuit design approaches. The GaAs MESFET depletion-mode n-channel technology employs 0.2- mu m e-beam defined gates, air-bridge interconnects for low capacitance, and molecular beam epitaxy (MBE) to grow the channel layers. The average threshold voltage of the resulting FETs is -0.6 V, and the extrinsic transconductance is approximately 500 mS/mm. H/sub 21/ measurements on individual devices yield an extrapolated f/sub T/ of approximately 8 GHz. The small-signal equivalent circuit model of a 50- mu m-wide device, derived from the measured S-parameters, is shown, and the resulting element values are presented.<> View full abstract»

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  • A 50 MIPS (peak) 32/64 b microprocessor

    Page(s): 76 - 77
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    An RISC (reduced-instruction-set-computer) microprocessor is described that, subject to data dependencies, can issue one 32-b instruction every 20-ns cycle to achieve peak performance of 50 MIPS (million instructions per second) for worst-case process and operating conditions. The chip includes a 64-b by 32-b general-purpose register file, a 22-b by 32-b privileged-register file, a 1 kB eight-way-associative virtual instruction cache, a 2-kB direct-mapped write-through physical data cache, an 8-entry fully associative instruction address translation buffer, a 32-entry fully associative data address translation buffer, a 10-entry by 64-b output data FIFO, 3-entry by 64-b instruction input FIFO, a 2-entry by 64-b data input FIFO, hardware support for multiprocessing, and a heavily pipelined integer execution unit. Although the execution unit has a 32-b datapath, the data cache, external interface, and register file are organized by 64 b to maximize data transfer rates and to allow single-cache issue of all double-precision instructions. The chip is fabricated in a 1.5- mu m drawn n-well double-metal CMOS process. It contains 294353 transistors, of which 135680 are in the cache arrays, measures 14.5 mm*9.5 mm, and is mounted in a 224-pin surface-mount leaded chip carrier. Power dissipation is 9 W at a 20 ns cycle time.<> View full abstract»

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  • A 64 b RISC microprocessor for a parallel computer system

    Page(s): 78 - 79
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    A description is given of a microprocessor that is designed as a processing element (PE) of a parallel computer system, executing a 64-b floating-point ADD/SUB/MULT in 50 ns and a DIV in 350 ns because of its pipelined structure and dedicated floating-point blocks. The processor employs RISC (reduced-instruction-set-computer) architecture and executes most of its 47 instructions in one 50-ns cycle. The chip is fabricated in 1.2- mu m n-well CMOS technology and contains 440 K transistors in a 14.4*13.5-mm/sup 2/ die. The processor provides high-speed double-precision floating-point operation, high reliability in data handling, communication capability between PEs and the host controller device, and hardware support for efficient code generation by the compiler. The maximum performance of the processor is 20 MFLOPS (million floating-point operations per second) or 20 MIPS (million instructions per second). Typical performance is 4 MFLOPS, measured during execution of Gaussian elimination operation. The major characteristics and performance of the processor are summarized.<> View full abstract»

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  • CMOS implementation of a 32 b computer

    Page(s): 80 - 81
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    A four-chip custom VLSI implementation of a 32-b computer comprised of a CPU, a secondary cache controller, a floating-point accelerator, and a clock generator is described. It operates at a cycle time of 28 ns and is compatible with an existing computer architecture. The chip set is fabricated in a 1.5- mu m n-well, double-layer-metal CMOS process and includes over 650000 transistors. The CPU is a six-level pipeline engine built around three semiautonomous pipes. These provide simultaneous instruction prefetch and decode, specifier decode and execution, memory management, and I/O access. The CPU averages nine cycles/instruction on typical benchmarks. Chip functionality is verified through test vectors at the pins, with stuck-at fault coverage greater than 95%, and complete control store and cache tests. Summaries of process characteristics and physical specifications are presented.<> View full abstract»

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  • 1989 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. 36th ISSCC. First Edition [front cover]

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  • A 30 MIPS VLSI CPU

    Page(s): 82 - 83
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    A description is given of a VLSI CPU which implements an existing 32-b architecture with a set of 140 instructions, most of which can be executed within one effective clock cycle. The device is fabricated in an nMOS process with three metal layers having minimum metal-1 line width of 1.5 mu m and drawn device lengths of 1.7 mu m. The die, containing 183000 transistors, is 1.4 cm*1.4 cm. The CPU directly addresses external SRAMs organized as a two-way set-associative split 512-kb-instruction/512-kb-data cache. Separate instruction and data paths allow for concurrent overlapped cache memory access. Chip specifications are presented, and the CPU data path is shown.<> View full abstract»

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  • A 20 MIPS sustained 32 b CMOS microprocessor with 64 b data bus

    Page(s): 84 - 85
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    The authors describe a full-custom 32-b microprocessor which uses a 1.5- mu m drawn n-well CMOS technology with single polycide and two levels of metal. The die size is 7.76 mm*6.21 mm and contains 180 k transistors, of which 150 k are used in the cache or register file. The CPU executes an RISC instruction set with simple and regular encoding. The chip has been designed for operation at 20 MIPS (million instructions per second), running large benchmarks in a complete system. Power dissipation at 25 degrees C with a 5-V supply is under 3 W. The chip has 136 signal, 16 power, and 16 ground pads and is packaged in a 176-pin plastic pin-grid-array package with eight decoupling capacitors. The CPU pipeline and machine organization and the instruction fetch pipestage are shown.<> View full abstract»

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  • Frame interline transfer CCD sensor for HDTV camera

    Page(s): 88 - 89
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    The authors describe the development of a HDTV (high-definition television) CCD (charge-coupled device) imager meeting the requirements for a practical color TV camera implemented with three CCD chips. They present a frame interline transfer CCD image sensor (FIT CCD), with 1258(H)*1035(V) pixels, that uses a poly-Si/Al double-layer transfer gate and p/sup +/-floating-island isolation. The saturation current of the present FIT CCD is 900 nA up to 625 kHz, whereas that of the conventional FIT CCD is fairly poor even at 300 kHz. The high transfer speed results from reduction of gate resistance. The photoconversion characteristics measured at a transfer frequency of 625 kHz show that the sensitivity reaches 50 nA/lx. The measured characteristics of the image sensor meet practical HDTV three-chip camera requirements.<> View full abstract»

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  • A 1/3" format image sensor with refractory metal light shield for color video applications

    Page(s): 90 - 91
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    The authors report results obtained on a full-color interline transfer CCD (charged-coupled device) image sensor with pixel dimensions of 8.6 mu m(H)*6.8 mu m(V) using 1.2- mu m design rules and a two-phase, single-polysilicon-per-phase technology. In order to reduce image smear and to provide suitable topography for integral color filters, a refractory light shield with a flowed glass overlayer was incorporated. The basic sensor and pixel architecture is shown. Image smear as a percent of full well, measured with 10% vertical illumination at saturated intensity, is shown as a function of wavelength. Smear is lowest at short wavelengths but is at an acceptable level for applications with controlled illumination.<> View full abstract»

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  • A DSP-based watthour meter

    Page(s): 92 - 93
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    A high-accuracy, three-phase electronic watthour meter, implemented in a 3.5- mu m double-poly CMOS technology, is described. It receives inputs from voltage and current sensors, measures both real and reactive power, and outputs pulses whose rate is proportional to energy flow. The meter is accurate to 0.3% of reading over 3.5 decades. A block diagram is presented, and the device functions are described. The DSP (digital signal processor) is developed as a macro cell with customized ROM/RAM. It has a 16-bit data path which can shift N bits and accumulate in one clock cycle. Both scalar and variable multiplications are possible.<> View full abstract»

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  • An abuttable CCD imager for visible and X-ray focal plane arrays

    Page(s): 94 - 95
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    Large multichip arrays for close-abutted CCDs (charged-coupled devices) are needed for surveillance applications in the visible band and for X-ray astronomy missions such as the Advanced X-ray Astrophysics Facility and the ASTRO-D satellite. A 420*420 pixel frame-transfer CCD imager which is designed to be abutted to other imagers on three sides so that arrays of 2*N chips can be constructed has been developed. A three-phase, triple-poly, buried-channel process is used, and the die size is 12 mm*20 mm. The arrays provide low-noise readout circuitry and high charge-transfer efficiency at low charge levels, critical requirements for both of the above applications. The device has also been shown to be suitable as a soft X-ray imager operating in a spectroscopic mode.<> View full abstract»

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  • A 310 k pixel bipolar imager (BASIS)

    Page(s): 96 - 97
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    A bipolar imager with an amplification function in each pixel has been developed using BiCMOS technology. The imager, which stores photocarriers in the base regions of the bipolar transistor pixels, is called the base-stored image sensor (BASIS). BASIS-type devices have been faced with three problems: (1) a reset transistor is needed in each pixel to initialize base voltage; (2) nonuniformity of offset voltage appears as fixed pattern noise; and (3) blooming is induced by intense light. Effective methods of dealing with these problems have been found. A BASIS imager with 310 k pixels in a 2/3-in optical format is described. The device specifications and characteristics of the imager are summarized.<> View full abstract»

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  • Merged CMOS/bipolar current switch logic

    Page(s): 112 - 113
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    Merged CMOS/bipolar logic (MCSL) is introduced and applied to a BiCMOS ripple adder. the adder shows bipolar performance without additional circuits for level conversion at the input. In contrast to a pure bipolar solution, the area and power are reduced by 50% for each bit. The advantage in area results from the smaller number of transistors and the smaller spacing of the MOS part. Only 28 transistors in comparison to 48 transistors, considering the emitter-follower and level shifter, are necessary for each bit. The advantage in power results from the smaller number of current paths. Only two gate and four emitter-follower currents rather than four gate and eight emitter-follower currents are necessary. Comparison to a pure CMOS adder cell shows a speed improvement by a factor of 5 with only a threefold increase in area.<> View full abstract»

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  • A single-ended BiCMOS sense circuit for digital circuits

    Page(s): 114 - 115
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    The authors present a fast single-ended BiCMOS sense circuit with CMOS output levels which is noise-insensitive enough to be used in a CMOS environment. A bipolar transistor is used in common-emitter configuration. Assuming that the bipolar transistor is conducting current, yet not saturated, a small voltage swing at the base is enough to turn the transistor off, and the collector voltage rises rapidly. An analog current mirror is used to prevent the bipolar transistor from saturating while maintaining a CMOS low-output voltage and to provide noise immunity. The full implementation of the sense circuit is shown.<> View full abstract»

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  • A BiCMOS logic gate with positive feedback

    Page(s): 116 - 117
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    It is noted that, as BiCMOS process technology is refined, the supply voltage must be reduced due to the lower endurance voltage of the devices and the larger power dissipation of the LSI chips. As the MOS drain current decreases with supply voltage, the base current from the MOS in a BiCMOS logic gate should then be sufficient for high-speed switching. Also, as the threshold voltage of the MOS becomes lower, a full logic swing function is necessary, even for BiCMOS gates, to ensure that a DC current does not flow in the next gate. These problems were solved with a BiCMOS logic gate with positive feedback, which was fabricated using a 0.5- mu m BiCMOS device and applied to a channelless gate array for a high-speed processor. Characteristics of the proposed logic gates are summarized. Experimental t/sub pd/ and P/sub d/ versus C/sub L/ characteristics for the three-input NAND at 4-V supply voltage are shown.<> View full abstract»

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  • A 76 MHz programmable logic sequencer

    Page(s): 118 - 119
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    The authors describe a BiCMOS programmable logic sequencer which provides reduced power, has functional density and flexibility similar to that of CMOS, and maintains speed as high as that of bipolar devices. The device is organized as 16 inputs, 48 product terms, and 8 registered outputs. Both logic AND and OR arrays are designed for user-programmability, enabling any chosen product term to be shared as a common sum-of-products by all of the outputs without resorting to a large number of product terms. A separate BiCMOS programming path test chip, compatible with this device, was manufactured simultaneously and evaluated separately. The equivalent gate count for this device is approximately 1000 gates. A maximum operating frequency of 76 Mhz, with 6-ns clock to output delay and 7-ns input setup time at a power dissipation of 370 mW, has been achieved. The process used to fabricate this device is a merged bipolar and CMOS technology featuring 1.9- mu m L/sub eff/ and 1.2- mu m*3- mu m emitter, three-layer metal and single-layer polycide for interconnections, TiW fuses, PtSi Schottky diodes, and polysilicon resistors.<> View full abstract»

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  • BiCMOS current source reference network for ULSI BiCMOS with ECL circuitry

    Page(s): 120 - 121
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    A BiCMOS current source reference network which eliminates the impact of DC power supply voltage drops on the operation of ECL (emitter coupled logic) circuits is described. This is essential for implementing ECL design techniques in ULSI BiCMOS circuits. Using the current source network, reference voltages are generated locally, so that the ECL voltage references are correctly referenced to the local power supply potentials. A power-supply-insensitive bandgap reference generator is used to generate precision on-chip voltage references and current sources. The bandgap reference circuit uses both MOS and bipolar transistors and is much simpler than a similar design using bipolar-only circuitry. The micrograph of the test chip containing the bandgap circuit nd BiCMOS op amp analog drivers is shown. The drivers are designed for multiple-reference-level regeneration. The test chip has been fabricated using a 0.8- mu m BiCMOS process. The typical characteristics of the bandgap circuit and the analog driver are shown.<> View full abstract»

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  • 500 k transistor custom BiCMOS LSI using automated macrocell design

    Page(s): 122 - 123
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    A high-density and quick-turnaround macrocell design method for custom VLSIs is applied to a 500 k-transistor protocol control chip, resulting in a density of about 4000 transistors/mm/sup 2/ using 0.8- mu m BiCMOS technology. An automated adaptive macrocell and a short-time custom VLSI design methodology were developed to make the logic and physical design more adaptable by offering greater variety of bit width, word length, circuit type, and signal terminals. The adaptive macrocell generation procedure consists of a logical description and a physical description with minimum information on the composition of complete macrocells, suitable for all specific uses. The variables providing adaptability are parameterized in this procedure, which is hierarchically described by network information among leaf cells or submacrocells, together with their topological placement information, permitting the adaptive macrocell to be generated automatically. An example of an ALU (arithmetic logic unit) circuit generated as a data-path submacrocell is shown. To verify the effectiveness of the proposed method, various kinds of macrocells were generated and fabricated using the 0.8- mu m, double-metal BiCMOS technology. A packet communication control circuit supporting X.25-based layer 2 and 3 protocols, which was designed by this method, is presented.<> View full abstract»

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  • A 70 MHz 32 b microprocessor with 1.0 mu m BiCMOS macrocell library

    Page(s): 124 - 125
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    A 70-MHz, 32-b microprocessor fabricated using BiCMOS macrocells is described. The chip contains about 529 k transistors, 521 k MOS transistors (98.5%), and 8 k bipolar transistors (1.5%). This small number of bipolar transistors increases the speed of the microprocessor chip to 70 MHz (40 MHz worst case), without increasing chip size. The macrocell design strategy is to increase integration density by using CMOS-based macrocells, reduce interchip communications, and accelerate the critical path by using bipolar drivers and sense circuits without increasing the total chip size. The BiCMOS device characteristics and chip specifications are given along with the macrocell specifications.<> View full abstract»

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  • A 16 Mb mask ROM with programmable redundancy

    Page(s): 128 - 129
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    In response to demands for a mask ROM with large bit capacity, a 1M-word*16 bit mask ROM with 120-ns access time has been fabricated. A programmable redundancy technique utilizes electrically fusible polysilicon links with the secondary breakdown mechanism of a MOSFET for high production yield and small chip area. The memory cell matrix arranged in 8192 rows*2048 columns and is divided into four blocks by two sets of row decoders in order to reduce word line delay. The redundancy cell array is composed of 8 rows*256 columns which can replace four defective quarter-rows. The mask ROM is fabricated in single-polysilicon single-aluminium twin-well CMOS technology with 0.7- mu m photolithography for high bit density. The process parameters and design features of the mask ROM are given together with a block diagram.<> View full abstract»

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