IEEE.org| IEEE Xplore Digital Library| IEEE Standards| IEEE Spectrum| More Sites

Cart (Loading....) | Create Account | Sign In

Author Search^beta | Advanced Search | Preferences | | More Search Options

Browse Conference Publications > Test Conference, 2002. Proceed ...

Test Conference, 2002. Proceedings. International

| Create Account

IEEE Account

Change Username/Password
Update Address

Purchase Details

Payment Options
Order History
Access Purchased Documents

Profile Information

Communications Preferences
Profession and Education
Technical Interests

Need Help?

US & Canada: +1 800 678 4333
Worldwide: +1 732 981 0060
Contact & Support

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.

Please enter a valid username or password.

For Institutional Users:

More Search Options

Test Conference, 2002. Proceedings. International

Date 10-10 Oct. 2002

Quick Links

Filter Results

You have selected:

You have selected:

You have selected:

Title History

Proceedings International Test Conference 2002 (Cat. No.02CH37382)

Author index

Panel: "board test and ITC: what does the future hold?"

Position statement: TAPs all over my chips

A scalable, low cost design-for-test architecture for UltraSPARC™ chip multi-processors

The role of test in a highly outsourced business model

High current DPS architecture for sort test challenge

Outsourcing test without standards?

A novel fault injection method for system verification based on FPGA boundary scan architecture

An open architecture for semiconductor test: enablers and challenges

Evaluating ATE features in terms of test escape rates and other cost of test culprits

Board test: wanted dead or alive

Efficient design of system test: a layered architecture

An implementation of IEEE 1149.1 to avoid timing violations and other practical in-compliance improvements

Wafer/package test mix for optimal defect detection

On the use of k-tuples for SoC test schedule representation

A multi-language goal-tree based functional test planning system

What a device interface board really costs: an evaluation of technical considerations for testing products operating in the Gigabit region

On the accuracy of jitter separation from bit error rate function

Test setup simulation - a high-performance VHDL-based virtual test solution meeting industrial requirements

An ATPG for threshold testing: obtaining acceptable yield in future processes

Testing wireless local area network transceiver ICs at 5GHz

Compensation of transmission line loss for Gbit/s test on ATEs

What can IC test teach system test?

Re-using DFT logic for functional and silicon debugging test

IEEE Account

Purchase Details

Profile Information

Need Help?