Proceedings. International Test Conference

10-10 Oct. 2002

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  • Proceedings International Test Conference 2002 (Cat. No.02CH37382)

    Publication Year: 2002
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    Freely Available from IEEE
  • Power driven chaining of flip-flops in scan architectures

    Publication Year: 2002, Page(s):796 - 803
    Cited by:  Papers (47)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (599 KB) | HTML iconHTML

    Power consumption during scan testing is becoming a primary concern. In this paper, we present a novel approach for scan cell ordering which significantly reduces the power consumed during scan testing. The proposed approach is based on the use of a two-step heuristic procedure that can be exploited by any chip layout program during scan flip-flops placement and routing. The proposed approach work... View full abstract»

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  • Author index

    Publication Year: 2002, Page(s):1249 - 1250
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    Freely Available from IEEE
  • Test coverage models for system test?

    Publication Year: 2002
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (75 KB) | HTML iconHTML

    Summary form only given. In the world of IC testing, efficiency measurements are based on test coverage of modeled faults, often stuck at faults. While this has been effective at the chip level to improve the quality of chip testing, the question is how can this be transferred to the system test level? At the system level we are faced with several potential complications in measuring the quality o... View full abstract»

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  • Can IC test learn from how a tester is tested

    Publication Year: 2002
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (81 KB) | HTML iconHTML

    Summary form only given. A tester as well as an IC is a system at different abstraction levels. The testing of each of these systems should contain individual component testing as well as a full system level functional test to ensure its functional correctness. A full functional test of IC should be done regardless of the fault coverage of individual blocks and test methodology including DFT, stru... View full abstract»

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  • Is it rocket science?

    Publication Year: 2002
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (40 KB) | HTML iconHTML

    Summary form only given. This article gives a general overview of system test. Topics covered include: chip test; board test; integrated system test; high integrity/value systems; field service; diagnostics; false failures; and spares. View full abstract»

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  • TAPS all over my chip! So now what do I do?

    Publication Year: 2002
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (38 KB) | HTML iconHTML

    Summary form only given. The test access port (TAP) and associated controller, standardized in IEEE std. 1149.1, is often used to control a wide variety of functions. For example, several existing cores use the TAP and associated controller to control internal test (e.g. logic-BIST) and debug (e.g. scan dumping) functionality. It is also common to see multiple of these cores, each with their own T... View full abstract»

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  • Position statement: TAPs all over my chips

    Publication Year: 2002
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (85 KB) | HTML iconHTML

    Summary form only given. An increasing number of system-on-chip (SoC) application-specific integrated circuits (ASICs) have more than one embedded processor with a test access port (TAP). A processor's TAP facilitates a hardware interface to a software development/debug tool. The author presents a technique whereby embedded TAPs can be accessed one at a time via a single TAP consisting of four or ... View full abstract»

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  • TAPs all over my chips

    Publication Year: 2002
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (61 KB) | HTML iconHTML

    Summary form only given. This article discusses chip test access ports (TAPs). Topics covered include: embedded core testing; chip TAP number; IEEE1149.1 standard; debug and diagnostics; internal TAP controllers; and compliance standards. View full abstract»

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  • Good scan = good quality level? Well, it depends

    Publication Year: 2002
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (78 KB) | HTML iconHTML

    Summary form only given. Quality can be defined as "a degree of excellence". In practice, we use testing as a measure of the outgoing quality of devices. The problem is that there is not a one-to-one correlation between test and quality. Just because a unit is tested doesn't guarantee that it is defect-free. Similarly, "guaranteed-by-design" functionality, usually isn't. So, what does it mean when... View full abstract»

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  • Mixed-signal BIST: fact or fiction

    Publication Year: 2002
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (86 KB) | HTML iconHTML

    Summary form only given. Most of today's SoCs embed complex analog and mixed-signal cores. BIST has been seen as one of the most promising potential solutions for embedded mixed-signal cores. But, the viability of mixed-signal BIST as a credible and general-purpose test solution has always been questioned for the past decade. It has been subject to many success stories and several failures and dis... View full abstract»

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  • Mixed-signal BIST: fact or fiction

    Publication Year: 2002
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (73 KB) | HTML iconHTML

    Summary form only given. Embedded test is essential for many of today's high-speed electronic designs that involve state-of-the-art silicon processes. Attempting to perform timing and frequency measurements across the chip I/O is fraught with parasitic interconnect issues, leading to excessive noise pick-up, asymmetrical delays and uneven incident/reflection levels. Interestingly enough, the probl... View full abstract»

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  • IC mixed-signal BIST: separating facts from fiction

    Publication Year: 2002
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (90 KB) | HTML iconHTML

    Summary form only given. BIST, by definition, requires on-chip generation of the stimulus, and on-chip analysis of the response, sufficient to produce a pass/fail result or a series of bits that any tester can compare bit-wise to the expected bit values. Many so-called on-chip mixed-signal built-in self-test (MS-BIST) approaches in fact require the ATE to supply the stimulus (analog waveform, or s... View full abstract»

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  • Mission impossible? Open architecture ATE

    Publication Year: 2002
    Cited by:  Papers (2)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (59 KB) | HTML iconHTML

    Summary form only given. A premise behind the open architecture system is to have a single set of hardware and software standards across the test industry, allowing instrumentation to be exchanged between ATE supplier boundaries. This paper asks whether the ATE suppliers will cooperate to set and maintain these standards while maintaining competition, and if not, looks at whether there is a suffic... View full abstract»

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  • Mission possible? Open architecture ATE

    Publication Year: 2002
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (83 KB) | HTML iconHTML

    Summary form only given. The current ATE business model is on a path to making test unaffordable. There are several competing technologies, and no synergy between platforms. Adopting an open standard similar to the PC business model could offer significant advantage to both test equipment suppliers and users. ATE instrument solutions implemented in the VXI (VME extensions for instrumentation) and ... View full abstract»

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  • Is an open architecture tester really achievable?

    Publication Year: 2002
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (32 KB) | HTML iconHTML

    Summary form only given. Management of tester technology has been a real challenge with Motorola's diverse product portfolio. Global support for multiple tester hardware architectures and operating systems is very expensive, difficult, and time consuming. Migration to new proprietary tester platforms requires massive efforts from design, test engineering, production, maintenance, and other areas. ... View full abstract»

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  • The consequences of an open ATE architecture

    Publication Year: 2002
    Cited by:  Papers (4)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (69 KB) | HTML iconHTML

    Summary form only given. It is clear that the time for a common, open ATE has arrived. The high level of technology integration and modularity make an open architecture feasible. The technical and economic challenges involved in testing system-on-a-chip (SoC) designs provide the needed driving force to make the common, open ATE architecture not only feasible but also highly desirable. Deployment o... View full abstract»

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  • An open architecture for semiconductor test: enablers and challenges

    Publication Year: 2002
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (74 KB)

    Summary form only given. The semiconductor test equipment industry has a history of being dominated by proprietary architectures that race to keep pace with increasing device complexity, device performance, and cost pressures. However, recent ATE design trends are resulting in modular hardware and software architectures with single board digital and analog instruments that reside in test head base... View full abstract»

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  • The role of test in a highly outsourced business model

    Publication Year: 2002
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (54 KB) | HTML iconHTML

    Summary form only given. The continuous pace of technical innovation in the semiconductor industry is driving development and manufacturing infrastructure costs to record levels, companies are responding by adopting new business models. Parts of the manufacturing flow, many of the development tools, and much of the IP are commonly outsourced by virtually all IC suppliers. The impact of this busine... View full abstract»

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  • The yield of test outsourcing

    Publication Year: 2002
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (49 KB) | HTML iconHTML

    Summary form only given. Many ways to outsource test activities has been explored recently. Often subcontractors have been employed to design portion of devices or entire circuits. Often it is also discovered that transferring DFT and test methodologies outside the originating company is critical. The efficiency of test development, and also the quality of product test can be affected. Reaching th... View full abstract»

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  • Outsourcing test without standards?

    Publication Year: 2002
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (70 KB) | HTML iconHTML

    Summary form only given. Within the product cycle of a System on Chip (SoC) there are various opportunities to outsource some of the tasks. For many years the manufacturing process has been subject separation from the product development. The author identifies the integrated device manufacturers (IDM) who develop and manufacture new chips. On the other side there are companies focusing on product ... View full abstract»

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  • Test and repair of embedded flash memories

    Publication Year: 2002
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (64 KB) | HTML iconHTML

    Summary form only given. Flash and EEPROM memories are now embedded in a large number of specific applications requiring a broad range of memory sizes. If full parallel access is possible the flash memory should be tested as a stand-alone memory. Controllability and observability are optimum, making test and characterization faster and easier. Unfortunately this approach results in an unacceptable... View full abstract»

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  • Test time impact of redundancy repair in embedded flash memory

    Publication Year: 2002
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (69 KB) | HTML iconHTML

    Summary form only given. Redundancy repair of high-density commodity flash memory is an effective technique to improve per-wafer yield by trading-off increased die size and increased time at wafer-probe for the ATE system to analyze the failing bits and make the necessary repairs. In embedded flash, where densities are typically much lower and test requirements more diverse, the benefit of redunda... View full abstract»

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  • Test and repair of non-volatile commodity and embedded memories (NAND flash memory)

    Publication Year: 2002
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (83 KB) | HTML iconHTML

    Summary form only given. The test time of the memory chip is a very important issue. It mainly depends on the program and erase time. NAND flash memories perform high speed programming and erasing. This high speed reprogramming scheme reduces the test cost. The program/erase endurance reliability is another important test issue. In order to perform at high reliability, NAND flash memories use ECC ... View full abstract»

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  • Test and repair of non-volatile commodity and embedded memories

    Publication Year: 2002
    Cited by:  Papers (2)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (81 KB) | HTML iconHTML

    Summary form only given. Semiconductor memory market has been driven by DRAM. However non-volatile memory market, flash memory as a representative, is growing remarkably because of its versatile application market such as cellular phone, PC memory card, silicon audio, digital still camera storage, automobile application with MCU and so forth. In terms of testing, it is quite different from DRAM. T... View full abstract»

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