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Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989

Date 15-18 May 1989

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Displaying Results 1 - 25 of 167
  • Proceedings of the IEEE 1989 Custom Integrated Circuits Conference (Cat. No.89CH2671-6)

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    The following topics are dealt with: floorplanning and routing; analog and digital design synthesis; programmable devices; data converters; mixed analog/digital applications; high-density/performance gate arrays; device modeling; computer elements; highly parallel architectures and neural nets; simulation; packaging and interfaces; telecommunication circuits; performance optimization; fabrication technology; CAD systems for designs and specifications; digital processors and speech recognition; test; complex module generation and assembly; video and image processing systematics; amplifiers and filters; and reliability View full abstract»

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  • A special purpose coprocessor supporting cell placement and floorplanning algorithms

    Page(s): 3.1/1 - 3.1/4
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    A coprocessor supporting a variety of placement and floorplanning algorithms is described. Without special hardware, the CPU time used by placement algorithms for net length computations can reach up to about 50% of the total run time. The proposed coprocessor architecture has special provisions for efficient net length computation which also allow concurrent execution with the main CPU. A prototype chip has been manufactured. The estimated speedup factor is about 40 for wire-length calculations. The chip can easily be integrated into current computer systems and usually requires only minimal changes to existing placement programs View full abstract»

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  • A new floorplanning algorithm for analog circuits

    Page(s): 3.2/1 - 3.2/4
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    The authors present a floorplanning algorithm based on a standard cell approach for analog circuits. The algorithm was developed to address a special analog requirements. Examples of filters and a high-voltage analog circuit are given, and the results look quite promising. Further research on the physical assembly includes the development of routing algorithms for sensitive analog signals View full abstract»

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  • A hierarchical floor-planning, placement, and routing tool for sea-of-gates designs

    Page(s): 3.3/1 - 3.3/4
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    The authors present an automatic layout system for designing large sea-of-gates gate arrays. This tool combines a floorplanning tool with an automatic placement and routing tool. It is designed to handle 250 K-gate arrays with special functional blocks such as RAM and ROM. It provides features for current processing, timing-driven layout, special clock distribution, and power distribution. The tool is currently being tested for designing the industry's most complex sea-of-gates gate arrays View full abstract»

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  • An interior point method for solving the global routing problem

    Page(s): 3.4/1 - 3.4/4
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    A linear programming (LP) model is presented for solving the global routing problem. This method simplifies the initial decomposition approach introduced by T.C. Hu and M.T. Shing (VLSI Layout: Theory and Design, IEEE Press, New York, p.144-52) to solve this problem. The authors reduce the complexity and size of the initial model by finding a smaller set of minimal and near-minimal rectilinear Steiner trees to route individual k-terminal nets. They then use a powerful dual affine interior point technique (Karmarkar algorithm) to solve the resulting (LP) problem. This solution approach is 5-10 times faster than standard Simplex-based approaches for solving LP problems and accelerates as the problem size increases. Numerical results are presented View full abstract»

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  • An efficient layer assignment algorithm for gridless switchbox routing

    Page(s): 3.6/1 - 3.6/5
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    A graph-theoretic algorithm is presented for the layer assignment and via minimization of a gridless switchbox routing. A concept called via propagation is used to facilitate the minimization of vias. The time complexity of the proposed algorithm is O(nlog n+K ), where n is the number of routing wire segments in the layout and K is the maximum number of vias that can occur. The approach achieves the minimum number of vias for several difficult switchbox problems View full abstract»

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  • LOGOPT-a multi-level logic synthesis and optimization system

    Page(s): 4.1/1 - 4.1/4
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    The author describes a logic optimization system that serves as the workhorse for three high level and one RTL-level synthesis systems. LOGOPT is capable of combinational and limited sequential circuit optimization and is particularly useful for resynthesis of netlists. The author describes the process of resynthesis with an effective approach to netlist partitioning for selective retention of hierarchy. This technique is invaluable for high-level synthesis and can also be used for partitioning existing netlists, so that troublesome or structured functions, such as arithmetic functions, can be efficiently implemented, either manually or with structured synthesis techniques. LOGOPT can optimize the glue-logic, while also performing netlist-netlist verification and timing optimization. Netlist-netlist verification coupled with the netlist partitioning can be used for verification of incremental changes, thus avoiding the need for simulation. The architecture of LOGOPT is described, and experimental data on the use of LOGOPT over a spectrum of actual designs is presented View full abstract»

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  • CHARM: a synthesis tool for high-level chip-architecture planning

    Page(s): 4.2/1 - 4.2/4
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    A description is given of CHARM, a chip-architecture planning tool for digital VLSI. From a behavioral description on the algorithmic level, a structural strip-architecture plan is synthesized. It uses a knowledge-based approach that incorporates heuristics and experience from industrial designers into the system. This is done by modeling the various chip-architecture principles using generic objects called schemes, which are instantiated during the design process. Evaluation is done by heuristic quality functions to determine the best-suited architecture. A blackboard architecture is an adequate structure for the prototype expert system. The quality of this expert system heavily depends on the success of the knowledge acquisition from experienced VLSI designers. A simplified design example is given View full abstract»

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  • ACACIA: the CMU analog design system

    Page(s): 4.3/1 - 4.3/5
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    A framework that automates the design of common analog integrated circuit modules has been developed. The framework, ACACIA, consists of three tools: OASYS, which transforms module specifications into sized schematics; ANAGRAM, which transforms sized schematics into mask geometry; and a graphics interface that facilitates automatic exploration of tradeoffs between design specifications by providing 3-D display of attainable performance surfaces View full abstract»

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  • From analog design description to layout: a new approach to analog silicon compilation

    Page(s): 4.4/1 - 4.4/4
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    A novel approach is presented to the silicon compilation of analog functional blocks. An algorithmic approach is adopted for the compiler and its structural components, including the synthesis, analog physical assembly, analog module generation, and device compilation. The approach is motivated by the need to aid the designer in assembling analog subsystems from a description of the design and parameterized leaf cells/operators. The results from an implementation that is being developed to compile high-performance, medium-speed sampled-data systems in BiCMOS technology are presented View full abstract»

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  • An integrated switched capacitor filter design system

    Page(s): 4.5/1 - 4.5/5
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    A CAD (computer-aided design) system integrating filter function design, circuit design, and layout is discussed. The core numerical optimization sizer uses full-accuracy models, including nonideal effects. Both interactive and highly automatic, the system allows completion of demanding, nonstandard switched-capacitor filter designs in one day View full abstract»

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  • Design automation system for analog circuits based on fuzzy logic

    Page(s): 4.6/1 - 4.6/4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB)  

    A design automation algorithm is proposed, and its effectiveness is evaluated by a prototype system. The goal is to obtain the near-optimum parameters for specifying the performance of the circuit. After the initial circuit parameters are calculated by a simple design technique, the performance is optimized. The system uses a circuit simulator to check the performance of the circuit. This performance is checked by using fuzzy logic. A production rule base is used for selecting a strategy to improve the performance. Using the prototype system, a differential amplifier was designed, with good results View full abstract»

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  • A 6 nsec CMOS EPLD with μW standby power

    Page(s): 5.1/1 - 5.1/4
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    A description is presented of a 28-pin CMOS EPROM (erasable programmable read-only memory)-based programmable logic device optimized for memory-address-decoding applications. A novel architecture provides high-speed operation at CMOS power levels. Reprogrammability and 100% testability of EPROM technology are added benefits. Active power is less than 25% of slower bipolar solutions, and die area is 74 mil2 View full abstract»

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  • A function specific EPLD for the PS/2 Micro Channel Bus adapter

    Page(s): 5.2/1 - 5.2/4
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    A description is given of VLSI devices that solve the complex interface problems between the Micro Channel Bus protocols of the IBM PS/2 system and add-on boards. One of the VLSI devices described makes use of programmability to allow system designers to customize their own interface through on-chip EPROM (erasable programmable read-only memory) bits. To make the task of interfacing to the Micro Channel straightforward for the system designer, accompanying software called McMap is provided. It is a table-driven program that will lead the system designer through the specifications. A custom version of his or her own interface can be specified through programming of the on-chip EPROM arrays. Adapter description files required by the PS/2 system are automatically generated for the user to install the board View full abstract»

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  • The effect of logic block complexity on area of programmable gate arrays

    Page(s): 5.3/1 - 5.3/5
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    The authors explore the tradeoff between the area of a programmable gate array (PGA) and the functionality of its logic block. A set of industrial circuits is implemented as PGAs using tools for technology mapping, placement, and routing. A simple model allows the exploration of a range of programming technologies and accounts for the area required by wiring. Experiments indicate that for combinational logic blocks implemented using lookup tables, the best number of inputs to use is between three and four, and that a D flip-flop should always be included in the logic block. These results are independent of the programming technology View full abstract»

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  • Electrical and geometrical circuit performance using an advanced sea-of-gates philosophy

    Page(s): 5.4/1 - 5.4/4
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    A sea-of-gates array has been designed to support random and regular logic and analog circuits. Its philosophy is to promote wiring and communication instead of packing as many transistors as possible on the array. At the global level, because of the saved routing area, densities as good as those obtained with a standard cell design style are achieved. Some important results on circuit densities and electrical performance are presented and discussed for the different circuit families. These results are compared with those obtained with other design styles. Several suitable CAD (computer-aided design) tools are presented View full abstract»

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  • A gate matrix deformation and three-dimensional maze routing for dense MOS module generation

    Page(s): 3.5/1 - 3.5/4
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    A two-stage method is proposed for generating dense MOS modules. The first stage is generation of dense placements of FETs (field-effect transistors) from the gate-matrix layouts, using a gate matrix deformation method. The deformation of gate-matrix layouts is guided by the design rules, using FETs with meander channel structures if needed. The second stage is routing of metal wires to connect FETs in modules. The authors have developed a three-dimensional maze router by extending the method to cope with arbitrary multilayer connections with user-defined costs for the connections in each layer. The costs can be used to assign desired priorities for each metal layer in the routing. This method results in about 65% reduction in chip area compared with the gate matrix method for typical examples using three- or four-layer connections View full abstract»

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  • A 12 ns, CMOS programmable logic device for combinatorial applications

    Page(s): 5.5/1 - 5.5/4
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    A 12-ns, 400-mW programmable logic device implemented in two-layer metal, 0.8-μm CMOS EPROM technology is presented. The device is optimized for combinatorial applications and provides programmable input macrocells for latched, registered, or combinatorial inputs. This device provides 1200 equivalent gates in a 28-pin package, with 13 inputs, 12 I/Os, one VCC, and two VSS pins. Each I/O pin, in addition to the programmable input register, has a product-term-controlled XOR gate for dynamic output polarity control and a control mux for output enable. The part has selective, nonvolatile power-down of unused circuitry. The sense amplifier is optimized for speed and power and is compensated for process, temperature, and pattern variations. The device uses a regulated substrate bias generator optimized for the process to improve latchup immunity and performance View full abstract»

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  • A 7.5 ns 350 mW BiCMOS PAL-type device

    Page(s): 5.6/1 - 5.6/4
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    A BiCMOS PAL-type device is described. It has a propagation delay of 7.5 ns and consumes 350 mW of power. The circuit has eight inputs, four bidirectional input/outputs and four registered outputs (known as 16R4 in databooks). The technology is a twin-well, merged bipolar and CMOS (BiCMOS) process. The minimum feature size is 1.2 μm View full abstract»

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  • A 15 ns 2500 gate highly flexible CHMOS EPLD

    Page(s): 5.7/1 - 5.7/4
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    A 2500-gate, 15-ns CMOS electrically programmable logic device (EPLD) with configurable inputs, expandable sum of products (SOP), and SOP implementation of control signals has been developed. Independent synchronous or asynchronous clocking of the inputs and outputs, plus both internal and pad feedback of each macrocell, makes this an extremely configurable 40-pin logic device. A combination of high speed, high density, and flexible architecture makes this device an ideal solution for high-speed microcomputer system design View full abstract»

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  • A 5000-gate CMOS EPLD with multiple logic and interconnect arrays

    Page(s): 5.8/1 - 5.8/4
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    A description is given of a CMOS electrically programmable logic device (EPLD) with over 220000 programmable elements organized into multiple logic array blocks (LABs) that communicate through a separate programmable interconnect array. Redundancy, for the first time ever in programmable logic devices, is implemented in both arrays to improve yield. Devices of different sizes can be easily constructed by varying the number of LABs and/or macrocells within one LAB. A 2× improvement in yield has been observed View full abstract»

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  • An 11 bit, 50 kSample/s CMOS A/D converter cell using a multislope integration technique

    Page(s): 6.2/1 - 6.2/4
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    An 11-bit, audio-speed analog-to-digital (A/D) converter for echo cancellation applications, which appears to consume the smallest chip area of any comparable converter, has been developed. It digitizes an analog input using the multislope integration technique, and requires one external capacitor. The DC and dynamic performance of the A/D converter were measured. The measured error plot indicates an integral nonlinearity of ±2 LSB (least significant bit) at 12 bits with no missing codes. A differential nonlinearity of ±0.5 LSB at 12 bits was measured using a statistical method. An S/N (signal-to-noise) versus input level measurement, obtained from the spectrum of the digitized output, indicates the effective dynamic linearity of the converter to be between 10 and 11 bits. The bandwidth is set by the sample-and-hold circuit View full abstract»

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  • An 8-bit two-step flash A/D converter for video applications

    Page(s): 6.3/1 - 6.3/4
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    A novel configuration for two-step analog-to-digital (A/D) flash conversion is described. The coarse and fine conversions are performed with a four-bit multiplexed flash converter, so only 15 comparators are necessary for an eight-bit converter. The D/A conversion and the subtraction required for the circuit operation are performed using the charge redistribution technique. A test chip, integrated with a 3-μm CMOS technology (area=3 mm2), has demonstrated the effectiveness of the proposed configuration View full abstract»

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  • CMOS low distortion sample and hold circuit for audio D/A converter

    Page(s): 6.5/1 - 6.5/4
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    A CMOS low distortion sample and hold circuit with total harmonic distortion of 0.01% for audio D/A (digital-to-analog) convertor has been developed, using a novel circuit architecture and high-speed operational amplifier. As an application of this technology to the audio field, an audio signal delay processing LSI with high-resolution A/D and D/A converters has been realized. The LSI has been fabricated using a 1.5-μm CMOS process and a die size of 18.5 mm2 View full abstract»

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  • A complete single supply CMOS 12 bit DAC

    Page(s): 6.6/1 - 6.6/4
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    A complete 12-bit voltage-out digital-to-analog converter that is fabricated in a 2-μm CMOS process and operates from a single 5-V supply is described. A sequence was developed to turn on current source segments in the two-dimensional array, which suppresses the INL (integral nonlinearity) due to the current source mismatch to ±1 LSB (least significant bit) and allows ±2 LSB of overall INL to be obtained without trimming the core. The guaranteed-monotonic output ranges from 0 to 2.56 V with a settling time of 3.0 μs View full abstract»

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