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On-Line Testing Workshop, 2002. Proceedings of the Eighth IEEE International

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On-Line Testing Workshop, 2002. Proceedings of the Eighth IEEE International

Date 10-10 July 2002

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Title History

Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002)

Author index

Design and implementation of a self-checking scheme for railway trackside systems

A BICS for CMOS opamps by monitoring the supply current peak

A system level approach in designing dual-duplex fault tolerant embedded systems

A ΣΔ A/D converter insensitive to SEU effects

On-line testing of embedded systems using optical probes: system modeling and probing technology

Using concurrent and semi-concurrent on-line testing during HLS: an adaptable approach

An architecture for self-healing digital systems

A March-based fault location algorithm for static random access memories

BIST-based delay-fault testing in FPGAs

Built-in-self-test of analogue circuits using optimised fault sets and transient response testing

A silicon-based yield gain evaluation methodology for embedded-SRAMs with different redundancy scenarios

Sequential n-detection criteria: keep it simple!

Fast and compact error correcting scheme for reliable multilevel flash memories

Defect-oriented analysis of memory BIST tests

A statistical sampler for a new on-line analog test method

The YATE fail-safe interface: the user's point of view

On-line error detection and correction in storage elements with cross-parity check

A BIST-based solution for the diagnosis of embedded memories adopting image processing techniques

A scan-BIST environment for testing embedded memories

Analysis of the equivalences and dominances of transient faults at the RT level

On-line monitor design of finite-state machines

Stop & go BIST

Robust data compression for analogue test outputs

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