By Topic

Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International

Date 3-6 Dec. 1989

Filter Results

Displaying Results 1 - 25 of 214
  • Long wavelength InAs/sub 0.2/Sb/sub 0.8/ detectors grown on patterned Si substrates by molecular beam epitaxy

    Page(s): 717 - 720
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (351 KB)  

    InAs/sub 0.2/Sb/sub 0.8/ photoconductive infrared detectors have been grown by molecular beam epitaxy (MBE) on patterned Si substrates. The MBE growth quality was evaluated using morphology analysis, absorption spectroscopy, and Hall measurements. The performances of InAsSb detectors grown in preetched Si wells, on Si mesas, and on unpatterned GaAs substrates are compared. It was found that the voltage responsivity of detectors grown in Si-wells was comparable to that of detectors grown simultaneously on unpatterned GaAs substrates. It is noted that this study is the first demonstration of a coplanar technology which is ideally suited for the monolithic integration of InAsSb-based Ir-detectors with Si charge coupled devices. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Picosecond photoconductivity using a graded bandgap Al/sub x/Ga/sub 1-x/As active detecting layer

    Page(s): 721 - 724
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (255 KB)  

    Improved responsivity for picosecond photoconductors is achieved by utilizing a graded bandgap Al/sub x/Ga/sub 1-x/As active detecting layer grown on a high-defect-density, low-temperature GaAs layer by MBE (molecular beam epitaxy). By taking advantage of the superior transport properties of the graded Al/sub x/Ga/sub 1-x/As layer, order-of-magnitude improvement in responsivity has been demonstrated, along with 2-6 times improvement in peak photocurrent response. This provides a capability to design photodetector speeds into the <10-ps regime.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low-noise and wide-bandwidth InGaAs/InAlAs superlattice APD

    Page(s): 725 - 728
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (469 KB)  

    An InGaAs-InAlAs superlattice avalanche photodiode (APD) was fabricated by MBE (molecular beam epitaxy), and impact ionization rates, excess multiplication noise, and high-frequency response were measured. The electron ionization rate ( alpha ) is enhanced by the large conduction band offset. The ratio of alpha / beta is as large as 29 at an electric field of 2.2*10/sup 5/ V/cm, where beta is the hole ionization rate. As a result of the enhanced ionization rate ratio, the excess multiplication noise is quite small and fits the theoretical curve with an effective ionization rate ratio of 0.05. The 3-dB bandwidth is 4 GHz at a multiplication factor of 16. This shows that the carrier pileup is negligible in a high electric field. The 3-dB bandwidth is limited not by the gain-bandwidth limit but by the electron diffusion time in the photoabsorption layer.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High reliability planar InGaAs avalanche photodiodes

    Page(s): 729 - 732
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (194 KB)  

    The reliability of planar buried-structure InGaAs APDs (avalanche photodiodes) for long-wavelength optical transmission systems was investigated. High-temperature aging tests were performed at 150 degrees C, 175 degrees C, and 200 degrees C, and two distinctive failure distributions (early failure and wear-out failure) were observed. The early failure is predicted to be caused by microplasma at the periphery of the guard ring junction, and the wear-out failure is related to the InP/SiN/sub x/ interface degradation by hot hole injection. The activation energy of the wear-out failure is estimated to be 1.15 eV, and the extrapolated median life at 50 degrees C exceeds 10/sup 8/ h. In the second step of the life testing, burn-in screening at 200 degrees C was shown to be effective in removing early failure and achieving long-term stability. 750000 h of device operation has been achieved without any failure at test temperatures of 125 degrees C and 150 degrees C, which indicates high reliability of the APDs.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Monolithically integrated In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As MSM-HEMT receiver grown by OMCVD on patterned InP substrates

    Page(s): 733 - 736
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (194 KB)  

    A long-wavelength receiver OEIC (optoelectronic integrated circuit) comprising an InAlAs-InGaAs MSM (metal-semiconductor-metal) detector and a InAlAs-InGaAs HEMT (high-electron mobility transistor) high-impedance preamplifier has been demonstrated. The layer structure was grown by LP-OMCVD (low-pressure organometallic chemical vapor deposition) on patterned InP substrates, which allowed independent optimization of the MSM detector and the HEMT preamplifier. The MSM detector showed the lowest leakage current (1 nA) ever reported with a 0.42 A/W responsivity, and the HEMT exhibited an external transconductance of 260 mS/mm. The bandwidth of the MSM-HEMT receiver was about 2 GHz. An excellent receiver response to 1.7 Gb/s NRZ random input signals has been obtained. The results reported strongly suggest that MSM-HEMT receivers have great potential for high-bit-rate optical-fiber communication systems.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Novel modulator structure permitting synchronous band filling of multiple quantum wells and extremely large phase shifts

    Page(s): 737 - 740
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (622 KB)  

    The authors have demonstrated synchronous band filling of multiple quantum wells using a novel blockaded reservoir and quantum-well electron transfer structure (BRAQWETS). The resulting electroabsorptive response per quantum well is not only stronger than that produced by the quantum confined Stark effect (QCSE) but is also free of induced absorption below the bandgap. The measured electrorefractive response shows that the maximum phase shift that can be achieved in one absorption length is one order of magnitude larger than what is possible with QCSE. Furthermore, the dependence of induced refractive index change on the applied voltage is essentially linear. Design criteria for very-high-performance modulators with picosecond intrinsic speed are also discussed. It is concluded that BRAQWETS provides a novel basis for high-performance electroabsorption modulators as well as low-loss phase modulators and interferometric amplitude modulators and switches. With suitable engineering, it will also be possible to construct multi-quantum-well lasers and detectors using BRAQWETS.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and test of an 8 GHz, 500 kW, side-coupled gyrotron

    Page(s): 747 - 749
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (157 KB)  

    The development of an 8-GHz gyrotron for lower hybrid heating of the FTU tokamak in Frascati, Italy is discussed. In the final system, 8 MW of RF power will be required, and the tokamak will operate for 1 s every 10 min. The gyrotrons will be required to operate into a 4:1 voltage standing wave ratio (VSWR). Because the RF antenna is a rectangular grill, the RF must be delivered to the tokamak in a rectangular, fundamental waveguide. The side-coupled approach has been developed to avoid complicated mode converters and filters. The RF is extracted transversely from the interaction circuit directly into the fundamental, rectangular waveguide. This represents a major departure from previous designs where the power is extracted axially in an overmoded, circular guide. Three tubes have been tested to date and another is being assembled for test. Test results are described as well as significant design changes that have occurred over the course of the program.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low velocity spread axis encircling electron beam forming system

    Page(s): 743 - 746
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (245 KB)  

    A novel electron gun and beamforming system for axis encircling electron beams has been designed. Simulations of the electron trajectories, including thermal velocities, have shown transverse and longitudinal velocity spreads of 0.5% and 1.6%, respectively, for a beam with an alpha of 2.1 and a 1.1 microperveance. The use of an asymmetric field reversal and an initially converging beam greatly reduces the length required for adiabatic compression of the beam. External control of the beam position and angular velocity makes it easy to optimize cyclotron-resonance-maser or peniotron interactions for differing radial cavity modes and cyclotron harmonics. Using this design, the beam radius, guiding center radius, annular width, alpha, and angular velocity can all be varied over a wide range by adjusting the gun electrode voltages and solenoid currents. The result is a short, flexible beamforming system which produces a low-velocity-spread, high-transverse-energy, axis-encircling electron beam. The computer codes used have yielded excellent correlation between simulation and experiment on a wide variety of gun designs.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The operation of a megawatt gyrotron in the submillimeter wave region

    Page(s): 751 - 754
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (374 KB)  

    The operation of a high-power, tunable gyrotron oscillator at wavelengths extending into the submillimeter-wave regime is reported. Using a 14-T Bitter magnet, frequencies from 141 GHz (TE/sub 15,2,1/ mode) up to 328 GHz (TE/sub 27,6,1/ mode) have been measured. As in earlier experiments, it was possible to step tune through a sequence of TE/sub m,p1/ modes over this range. From 198 GHz to 328 GHz, these modes corresponded to p=4, 5, and 6. Even though the cavity is highly overmoded at 328 GHz, output powers remain quite high, with a peak output power of 430 kW at 80 kV and 35 A. This corresponds to an efficiency of 15%. This is the highest power generated by a gyrotron in the submillimeter region. Even better results were obtained in the TE/sub 22,5,1/ mode at 267 GHz. A peak power of 600 kW was produced when operating at 80 kV and 35 A, for an efficiency of 21%. A detailed study of the TE/sub 16,2,1/ mode at 148 GHz has been made, and the beam parallel velocity was measured with a capacitive probe.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design considerations in achieving 1 MW CW operation with a whispering-gallery-mode gyrotron

    Page(s): 755 - 758
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (226 KB)  

    High-power, CW (continuous-wave) gyrotrons at frequencies in the range 100 GHz to 150 GHz are being developed for use in electron cyclotron heating applications. Early test vehicles have utilized a TE/sub 15,2,1/ interaction cavity and have achieved short-pulse power levels of 820 kW and average power levels of 80 kW at 140 GHz. Present tests are aimed at reaching 400 kW under CW operating conditions and up to 1 MW for short pulse durations. Work is also underway on modifications to the present design that will enable power levels of up to 1 MW CW to be achieved.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Cyclotron autoresonance maser amplifiers and oscillators

    Page(s): 759 - 762
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (343 KB)  

    The theory of the CARM (cyclotron autoresonance maser amplifier) and the design and simulation of (1) a 20-MW, 33-GHz, 400-kV CARM amplifier, (2) a 0.4-GW, 250-GHz, 2-MV CARM oscillator in a Bragg resonator, and (3) a 100-kV dielectric loaded CARM are presented. The CARM is a wideband device with high efficiency due to autoresonance for frequencies well above cutoff. The CARM can also withstand extremely high power due to the reduced attenuation from being far above cutoff. The large Doppler upshift results in a much weaker magnetic field requirement compared to the gyrotron, but it also leads to the need for a high-quality electron beam with a low axial velocity spread.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A self-aligned inverse-T gate fully overlapped LDD device for sub-half micron CMOS

    Page(s): 765 - 768
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB)  

    A novel self-aligned technique for fabricating inverse-T gate fully overlapped LDD (FOLD) MOSFETs is proposed. The technique uses an oxide or TiN buffer layer sandwiched in a polysilicon gate stack to act as an RIE (reactive ion etching) etch stop. Both the oxide and TiN exhibit good etch selectivities with respect to polysilicon. Therefore, a controllable, uniform polysilicon finger can be obtained to form the inverse-T structure. A 0.35- mu m n-channel inverse-T gate MOSFET with fully overlapped LDD (lightly doped drain) design has been fabricated and characterized. It is found that the inverse-T LDD device preserves the performance of a non-LDD device while providing reliability improvement similar to that of a conventional LDD device. The inverse-T LDD device is suitable for high-performance, high-reliability sub-half-micron device applications.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A self-aligned LDD/channel implanted ITLDD process with selectively-deposited poly gates for CMOS VLSI

    Page(s): 769 - 772
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (244 KB)  

    A novel inverse-T LDD (ITLDD) CMOS process has been developed as part of a submicron CMOS technology that features self-aligned LDD/channel implantation for improved hot-carrier protection. The resulting ITLDD device structures can be designed with very light n- and p-LDD (lightly doped drain) implantations. This leads to lower substrate current due to reduced compensation effects of the lightly doped LDD regions by the heavy channel doping profile. The use of selective polysilicon deposition rather than an incomplete polysilicon etchback process to define the inverse-T gate results in a simpler, more manufacturable process for the ITLDD structure.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A high performance and highly reliable dual gate CMOS with gate/n/sup -/ overlapped LDD applicable to the cryogenic operation

    Page(s): 773 - 776
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (393 KB)  

    A dual-gate CMOS structure has been developed which features an overlap LDD (lightly doped drain) NMOS with n/sup +/ poly gate and a surface channel PMOS with p/sup +/ poly gate whose source/drain and gate were salicided with low-resistance TiSi/sub 2/. The gate/n/sup -/ overlapped structure was fabricated by rotational oblique ion implantation. This CMOS structure can realize low-supply-voltage operation due to the small absolute value of threshold voltage without punchthrough. It is demonstrated that, using the overlap LDD NMOS, the circuit speed and the reliability can be improved, compared with the single and the conventional LDD NMOS. The cryogenic operation of the structure is examined.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 1/4- mu m LATID (LArge-Tilt-angle Implanted Drain) technology for 3.3-V operation

    Page(s): 777 - 780
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (358 KB)  

    3.3-V operation has been demonstrated for a 1/4- mu m MOSFET having a large-tilt-angle implanted drain (LATID) structure, which is developed by using ultrathin spacers to minimize the n/sup +/ gate overlap while keeping the n/sup -/ region fully overlapped with the gate. The 1/4- mu m LATID device achieves a high saturation transconductance of 200 mu S/ mu m and an excellent propagation delay time of 75 ps/stage (comparable to the device/circuit performance of single-S/D (source/drain) FETs), an improved device lifetime of over 300 years, a low gate-induced drain leakage (GIDL) of less than 0.1 pA/ mu m, and suppressed short-channel effects under 3.3-V operation. It is reconfirmed that the n/sup -/ LAT implant substantially reduces GIDL effects.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An integrated 0.5 mu m CMOS disposable TiN LDD/salicide spacer technology

    Page(s): 781 - 784
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (215 KB)  

    A novel disposable TiN LDD/salicide spacer process has been developed for a 0.5- mu m CMOS technology. Both LDD (lightly doped drain) and salicide definition are obtained using a single disposable TiN spacer. This process results in CMOS devices with low salicided junction leakage, reduced source/drain lateral diffusion, and shallow phosphorus n- and boron p-regions for improved short-channel behavior.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimization of amorphous layer thickness and junction depth on the pre-amorphization method for forming shallow-junction in silicon

    Page(s): 785 - 788
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (226 KB)  

    A 0.1- mu m-deep p/sup +/-n junction was formed by Si/sup +/ and Ge/sup +/ preamorphization methods. Both the thickness of the preamorphized layer and the junction depth were optimized systematically. It is found that channeling of 15-keV, 2*10/sup 15/-cm/sup -2/ dose BF/sub 2//sup +/ implantation is eliminated by a 40-nm-thick preamorphized layer formed by Si/sup +/ implantation and that the junction must be formed 70-90 nm deeper than the amorphous-crystal (a-c) interface for the Si/sup +/ case and 20 nm for the Ge/sup +/ case in order to reduce leakage current density J/sub 1/ to less than 1*10/sup -8/ A/cm/sup -2/. The advantage of the Ge/sup +/ case over the Si/sup +/ case is confirmed. The dependence of J/sub 1/ on the distance between the junction and a-c interface (x/sub j/-x/sub a/) was also investigated. It is confirmed that the preamorphized layer thickness influences the dependence of J/sub 1/ on x/sub j/-x/sub a/ for both Si/sup +/ and Ge/sup +/ preamorphizations.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Bipolar device design for high density high performance application

    Page(s): 791 - 794
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (203 KB)  

    An analysis of a loaded ECL (emitter coupled logic) gate fabricated in a modern bipolar process shows that the delay is dominated equally by intrinsic and extrinsic components. The design of technology to minimize these components is discussed. As device dimensions are reduced the extrinsic delay components dominate; these components can be minimized by optimizing packing density and using reduced ECL voltage swings. It is suggested that circuits of complexity of 100 K gates and delays of less than 20 ps will be possible in the near future.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Scaling rules for bipolar transistors in BiCMOS circuits

    Page(s): 795 - 798
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (427 KB)  

    Scaling rules for bipolar transistors in BiCMOS gates are derived such that the gates maintain their performance advantage over scaled CMOS implementations. These are compared with those for bipolar transistors in ECL (emitter coupled logic) gates and are found to be generally similar under realistic scaling assumptions, except for a conflict in the choice of the collector doping concentration. Bipolar transistors for BiCMOS drivers require a high collector doping concentration (typically higher than 5E16 cm/sup -3/) while ECL circuits require bipolar transistors with lower value for the collector doping concentration (typically lower than 2E16 cm/sup -3/).<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On the scaling property of trench isolation capacitance for advanced high-performance ECL circuits

    Page(s): 799 - 802
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (281 KB)  

    A detailed study on the scaling property of trench isolation capacitance for advanced high-performance bipolar applications is presented. Using two-dimensional numerical simulations, it is shown that depending on the particular trench used, the trench isolation capacitance has a distinct dependence on the trench width. The impact on the scaled-down high-performance ECL circuits is examined. It is concluded that the design and optimization of scaled-down devices and circuits would require an in-depth understanding of the trench isolation parasitics to realize the full potential of advanced technology.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Hot-electron-induced minority carrier generation in bipolar junction transistors

    Page(s): 803 - 806
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    The authors report the observation and analysis of minority carrier generation in the collector and the substrate of n-p-n bipolar junction transistors as a result of photons which are generated in the collector-base depletion region. Both the substrate current and the additional leakage current in an adjacent n/sup +/-p junction peak at V/sub BE/ approximately=0.8 V. In the authors' model of the phenomena, the photons induce carriers both in the depletion region and in the neutral region. The generated minority carriers in the neutral region diffuse and contribute to the substrate current and the junction leakage current.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A closed-form analysis of f/sub T/ for the bipolar transistor down to liquid nitrogen temperature

    Page(s): 807 - 810
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (364 KB)  

    A simple closed-form expression for f/sub T/ (cutoff frequency) down to liquid nitrogen temperature has been determined by examining the emitter-collector transit time, t/sub ec/, where f/sub T/=1/(2 pi t/sub ec/). This closed-form expression gives excellent agreement with measured values for polysilicon emitter n-p-n transistors which have been fabricated with Stanford's triple-diffused BiCMOS process. It is shown that the BJT (bipolar junction transistor) f/sub T/ behavior over temperature is primarily determined by only three terms: the base minority carrier storage time, the emitter minority carrier storage time, and the base-collector space-charge-layer storage time. The match of experimental data with the closed-form f/sub T/ expression shows that an increase in the base transit time in compensated BJT base regions at low temperature due to minority carrier trapping does occur and is the main reason for the degradation of f/sub T/ at temperatures lower than 150 K in the devices considered.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Pseudo-HBT with polysilicon emitter contact and an ultrashallow highly doped bases by photoepitaxy

    Page(s): 811 - 814
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (342 KB)  

    It is noted that reducing the base width to below 50 nm and increasing the base concentration to above 10/sup 19/ cm/sup -3/ are the key to high-speed pseudo-HBT (heterojunction bipolar transistor) operation at 77 K. To overcome the limitation on the base concentration due to tunneling, an emitter was fabricated with a reduced impurity concentration (4.4*10/sup 18/ cm/sup -3/) and a 55-nm ultrathin heavily doped base using a photoepitaxial growth technique. The device was free from tunneling current despite a base concentration of 1.2*10/sup 19/ cm/sup -3/. Current gain degradation at low temperatures was less than that of conventional devices. Heavily doped polysilicon between the medium-doped emitter layer and metal electrode improves the pseudo-HBT's current gain by about three times at 300 K and by 1.5 times at 77 K. The transit time due to this polysilicon layer, although large at 300 K, is negligible at 77 K.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Thin-film SOI technology: the solution to many submicron CMOS problems

    Page(s): 817 - 820
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB)  

    The performances of thin-film SOI (silicon-on-insulator) MOSFETs and CMOS circuits are presented. Attention is given to the SOI material, device properties, and design and processing. It is noted that this technology is extremely attractive for deep-submicron applications because of such properties as improved subthreshold slope, reduced short-channel effects, reduced electric fields, increased transconductance, and better immunity to soft errors. Front-end CMOS processing of thin films of SOI is also considerably simpler than bulk device processing. The competitiveness of TFSOI technology on the CMOS market is discussed.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Half-micron CMOS on ultra-thin silicon on insulator

    Page(s): 821 - 824
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (293 KB)  

    A 0.5- mu m CMOS technology on ultrathin SIMOX SOI (silicon-on-insulator) material with silicon film thickness of 80 nm is studied. When compared with bulk devices the SOI NMOS devices showed a slightly reduced current-drive-capability, a small negative differential output conductance at high gate bias, and a strongly reduced breakdown voltage. Floating-substrate effects remain significant even for SOI devices on ultrathin material. The hot-carrier degradation of the SOI NMOS devices was significantly enhanced by electron injection in the buried oxide layer. The performance of ring oscillators on SOI material was excellent. Furthermore, fully functional 2K SRAM circuits were fabricated. The main advantages of ultrathin-film SOI seem to be the improved circuit properties and the simplified fabrication technology. The reduction of the floating-body effects in the devices on ultrathin-film SOI is required to make SOI a competitor to bulk material for future deep submicron CMOS.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.