2017 IEEE North Atlantic Test Workshop (NATW)

8-10 May 2017

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Displaying Results 1 - 9 of 9
  • [Front cover]

    Publication Year: 2017, Page(s): c1
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  • Copyright notice

    Publication Year: 2017, Page(s): 1
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  • Message from the general chair

    Publication Year: 2017, Page(s):1 - 4
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  • Case study of bandwidth management in SoC testing

    Publication Year: 2017, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (263 KB) | HTML iconHTML

    The system-on-chip (SoC) designs encapsulate many disparate types of complex IP cores. Typically, the SoC test bandwidth (the total input/output scan ports at the SoC boundary) is much smaller than the total input/output scan channels of all cores. To test a SoC with limited test bandwidth, many test bandwidth management technologies are proposed in the past. In this paper, we use a case study to ... View full abstract»

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  • Peer pressure on identity: On requirements for disambiguating PUFs in noisy environment

    Publication Year: 2017, Page(s):1 - 4
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (647 KB) | HTML iconHTML

    The number of devices that are being connected by the Internet is growing rapidly and hence, safeguarding private information by incorporating hardware and software security measures has become crucial. Physically unclonable functions (PUFs) have been proposed to enable lightweight hardware security which uses the inherent manufacturing variations as a way to generate unique signatures. However, g... View full abstract»

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  • Manufacturer turned attacker: Dangers of stealthy trojans via threshold voltage manipulation

    Publication Year: 2017, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (612 KB) | HTML iconHTML

    Applications of Integrated Circuits (ICs) have become pervasive. A striking feature of the contemporary IC industry is that a very large and growing proportion of the IC foundries are now located offshore. While offshoring IC production reduces cost, it also creates a concern that the functionality of the circuits may be compromised by Trojans designed to cause malfunction at a select times. This ... View full abstract»

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  • Mitigating simple power analysis attacks on LSIB key logic

    Publication Year: 2017, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (829 KB) | HTML iconHTML

    Locking Segment Insertion Bits (LSIBs) have been proposed to secure access to on-chip embedded instruments in IEEE 1687 networks. LSIBs can be opened (or closed) only if the correct key value is applied to the LSIB's key logic circuit. Using gate-level simulations previously used for cryptographic circuits, we evaluate the susceptibility of several LSIB key logic designs to simple power analysis a... View full abstract»

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  • An enhanced approach to reduce test application time through limited shift operations in scan chains

    Publication Year: 2017, Page(s):1 - 4
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (665 KB) | HTML iconHTML

    Scan Chains in Design For Testability gained more prominence due to the increase in the complexity of the modern circuits. As the test time increases along with the number of memory elements in the circuit, new and improved methods are needed. Even though scan chains implementation effectively increases observability and controllability, a big portion of the time is wasted while shifting in and sh... View full abstract»

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  • Detecting a trojan die in 3D stacked integrated circuits

    Publication Year: 2017, Page(s):1 - 6
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    While 3D integrated circuits provide many security advantages, one disadvantage is the insertion of a Trojan die into the stack. In this paper, we explore a technique to detect an extra die through delay analysis. View full abstract»

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