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VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on

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VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on

Date 11-13 June 2002

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Title History

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

Author index

Improved film growth and flatband voltage control of ALD HfO₂ and Hf-Al-O with n⁺ poly-Si gates using chemical oxides and optimized post-annealing

Super-resolution enhancement method with phase-shifting mask available for random patterns

Fabrication of a novel strained SiGe:C-channel planar 55 nm nMOSFET for high-performance CMOS

An ultra-thin silicon nitride gate dielectric with oxygen-enriched interface (OI-SiN) for CMOS with EOT of 0.9 nm and beyond

Novel integration technologies for highly manufacturable 32 Mb FRAM

A strategy using a copper/low-k BEOL process to prevent negative-bias temperature instability (NBTI) in p-MOSFETs with ultra-thin gate oxide

Practical next generation solution for stand-alone and embedded DRAM capacitor

Highly manufacturable sub-100 nm DRAM integrated with full functionality

New guideline for hydrogen treatment in advanced system LSI

A ferroelectric analog associative memory technology employing hetero-gate floating-gate-MOS structure

MEMS technology: optical application, medical application and SOC application

UX6-100 nm generation CMOS integration technology with Cu/low-k interconnect

70 nm fully-depleted SOI CMOS using a new fabrication scheme: the spacer/replacer scheme

A 100 nm copper/low-k bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications

Integration of capacitor for sub-100-nm DRAM trench technology

Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs

The effects of substrate coupling on triggering uniformity and ESD failure threshold of fully silicided NMOS transistors

A novel 2-bit/cell MONOS memory device with a wrapped-control-gate structure that applies source-side hot-electron injection

Femto-second CMOS technology with high-k offset spacer and SiN gate dielectric with oxygen-enriched interface

50 nm-Gate All Around (GAA)-Silicon On Nothing (SON)-devices: a simple way to co-integration of GAA transistors within bulk MOSFET process

Effects of high-temperature forming gas anneal on HfO₂ MOSFET performance

Impact of Joule heating on scaling of deep sub-micron Cu/low-k interconnects

Mobility enhancement in strained Si NMOSFETs with HfO₂ gate dielectrics

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