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2016 International Conference on Field-Programmable Technology (FPT)

7-9 Dec. 2016

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Displaying Results 1 - 25 of 81
  • [Front matter]

    Publication Year: 2016, Page(s):1 - 5
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  • Content

    Publication Year: 2016, Page(s):1 - 4
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  • High-level synthesis - the right side of history

    Publication Year: 2016, Page(s): 1
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  • The configurable cloud - accelerating hyperscale datacenter services with FPGAs

    Publication Year: 2016, Page(s): 1
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  • FPGA as service in public Cloud: Why and how

    Publication Year: 2016, Page(s): 1
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  • Device

    Publication Year: 2016, Page(s): 1
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  • High density, low energy, magnetic tunnel junction based block RAMs for memory-rich FPGAs

    Publication Year: 2016, Page(s):4 - 11
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2053 KB)

    Many important applications demand large amounts of on-chip memory both to fully utilize an FPGA's computational capacity and to minimize energy-consuming off-chip memory accesses, leading some recent commercial FPGAs to add higher-capacity on-chip block RAMs (BRAMs). While memory is becoming more important to FPGA designs, SRAM scaling is becoming more difficult because of increasing device varia... View full abstract»

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  • Analysis of transient voltage fluctuations in FPGAs

    Publication Year: 2016, Page(s):12 - 19
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB) | HTML iconHTML

    Due to recent technology scaling trends and increased circuit complexity, process and runtime variabilities are becoming major threats for correct circuit operation. Among these, transient voltage fluctuations appear to be the most critical issue, accounting for the biggest component of timing margin, at increased cost. As various design and workload parameters have an impact on voltage fluctuatio... View full abstract»

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  • An energy-efficient near/sub-threshold FPGA interconnect architecture using dynamic voltage scaling and power-gating

    Publication Year: 2016, Page(s):20 - 27
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (959 KB) | HTML iconHTML

    The rapid development of the Internet-of-Things requires hardware that is both low-energy and flexible, and a near/sub-threshold FPGA is a very promising solution. In the design of near/sub-threshold FPGAs, the biggest challenge is reducing global interconnect energy, which is the most energy-consuming part in the entire FPGA. Dynamic voltage scaling is an effective technique in reducing energy, b... View full abstract»

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  • Architecture

    Publication Year: 2016, Page(s): 1
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  • Integer computations with soft GPGPU on FPGAs

    Publication Year: 2016, Page(s):28 - 35
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (531 KB) | HTML iconHTML

    This paper explores the capabilities and limitations of soft GPGPU-based computing on fixed-point arithmetic. The work is based on an existing soft GPU architecture which has been improved and extended to cover broader benchmarks. A generic ALU design for modern FPGA architectures is presented. The enhanced ISA includes conditional instructions and global atomic operations. We extended the tool fl... View full abstract»

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  • Network-attached FPGAs for data center applications

    Publication Year: 2016, Page(s):36 - 43
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (357 KB) | HTML iconHTML

    FPGAs (Field Programmable Gate Arrays) are making their way into data centers (DC). They are used as accelerators to boost the compute power of individual server nodes and to improve the overall power efficiency. However, this approach limits the number of FPGAs per node and hinders the acceleration of large-scale distributed applications. We propose a system architecture to deploy large-scale DC ... View full abstract»

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  • Hypervisor mechanisms to manage FPGA reconfigurable accelerators

    Publication Year: 2016, Page(s):44 - 52
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1188 KB) | HTML iconHTML

    In the last decade, the research on CPU-FPGA hybrid architectures has become a hot topic. One of the main challenges in this domain consists in efficiently and safely managing dynamic partial reconfiguration (DPR) resources. This paper focuses on the management of the reconfiguration by an hypervisor on an ARM-FPGA platform. Using the virtualization approach, virtual machines (VM) may access resou... View full abstract»

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  • Application

    Publication Year: 2016, Page(s): 1
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  • FPGA-based acceleration of FDAS module using OpenCL

    Publication Year: 2016, Page(s):53 - 60
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB) | HTML iconHTML

    The Square Kilometre Array (SKA) project will be the world largest radio telescope array. With the growth of the number of antennas, the signals that need to be processed increase dramatically. One import element of the SKA central signal processor (CSP) package is pulsar search. This paper focuses on the FPGA-based acceleration of the frequency-domain acceleration search (FDAS) module, part of SK... View full abstract»

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  • Automatic code generation of convolutional neural networks in FPGA implementation

    Publication Year: 2016, Page(s):61 - 68
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (822 KB) | HTML iconHTML

    Convolutional neural networks (CNNs) have gained great success in various computer vision applications. However, state-of-the-art CNN models are computation-intensive and hence are mainly processed on high performance processors like server CPUs and GPUs. Owing to the advantages of high performance, energy efficiency and reconfigurability, Field-Programmable Gate Arrays (FPGAs) have been widely ex... View full abstract»

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  • An efficient implementation of online arithmetic

    Publication Year: 2016, Page(s):69 - 76
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (674 KB) | HTML iconHTML

    We propose the first hardware implementation of standard arithmetic operators - addition, multiplication, and division - that utilises constant compute resource but allows numerical precision to be adjusted arbitrarily at run-time. Traditionally, precision must be set at design-time so that addition and multiplication, which calculate the least significant digit (LSD) of their results first, and d... View full abstract»

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  • Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC

    Publication Year: 2016, Page(s):77 - 84
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (597 KB) | HTML iconHTML

    Deep neural networks (DNNs) are widely used in data analytics, since they deliver state-of-the-art accuracies. Binarized neural networks (BNNs) are recently proposed optimized variant of DNNs. BNNs constraint network weight and/or neuron value to either +1 or -1, which is representable in 1 bit. This leads to dramatic algorithm efficiency improvement, due to reduction in the memory and computation... View full abstract»

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  • Random projections for scaling machine learning on FPGAs

    Publication Year: 2016, Page(s):85 - 92
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB) | HTML iconHTML

    Random projections have recently emerged as a powerful technique for large scale dimensionality reduction in machine learning applications. Crucially, the projection can be obtained from sparse probability distributions, enabling hardware implementations with little overhead. In this paper, we describe a Field-Programmable Gate Array (FPGA) implementation alongside a kernel adaptive filter (KAF) t... View full abstract»

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  • High-speed regular expression matching with pipelined automata

    Publication Year: 2016, Page(s):93 - 100
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB) | HTML iconHTML

    Pattern matching is a complex task which is widely used in network security monitoring applications. With the growing speed of network links, pattern matching architectures have to be improved in order to retain wire-speed processing. Multi-striding is a well-known technique on how to increase throughput of pattern matching architectures. In the paper we provide an analysis of scalability of multi... View full abstract»

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  • Reliability

    Publication Year: 2016, Page(s): 1
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  • Fine-grained module-based error recovery in FPGA-based TMR systems

    Publication Year: 2016, Page(s):101 - 108
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB) | HTML iconHTML

    Space processing applications deployed on SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to radiation-induced Single Event Upsets (SEUs). Compared with the well-known SEU mitigation solution - Triple Modular Redundancy (TMR) with configuration memory scrubbing - TMR with module-based error recovery (MER) is notably more energy efficient and responsive in repairing soft-errors in ... View full abstract»

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  • Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designs

    Publication Year: 2016, Page(s):109 - 116
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (386 KB) | HTML iconHTML

    High-Level Synthesis (HLS) has emerged as a leading technology to reduce the design time and complexity that is associated with reconfigurable systems. In order to maintain the productivity promised by HLS, it is important that the designer can debug the system in the context of the high-level code. Currently, software simulations offer a quick and familiar method to target logic and syntax bugs, ... View full abstract»

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  • A Programmable Configuration Controller for fault-tolerant applications

    Publication Year: 2016, Page(s):117 - 124
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (839 KB) | HTML iconHTML

    FPGAs are promising candidates for computational tasks in space applications. However, they are susceptible to radiation-induced errors, the most common failure being due to the corruption of their configuration memory. Module-based partial reconfiguration and frame-based scrubbing are the two most commonly used techniques for detecting and recovering from configuration memory errors. Both methods... View full abstract»

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  • High level synthesis (HLS)

    Publication Year: 2016, Page(s): 1
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