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Design Automation Conference, 2002. Proceedings. 39th

Date 10-14 June 2002

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  • Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)

    Publication Year: 2002
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  • PANEL: tools or users: which is the bigger bottleneck?

    Publication Year: 2002, Page(s):76 - 77
    Cited by:  Papers (1)
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  • PANEL: analog intellectual property: now? or never?

    Publication Year: 2002, Page(s):181 - 182
    Cited by:  Papers (2)
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  • Panel: nanometer design: what hurts next....?

    Publication Year: 2002, Page(s): 242
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  • Panel: whither (or wither?) ASIC handoff?

    Publication Year: 2002, Page(s):317 - 318
    Cited by:  Papers (1)
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  • Panel: unified tools for soc embedded systems: mission critical, mission impossible or mission irrelevant?

    Publication Year: 2002, Page(s): 479
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  • Panel: formal verification methods: getting around the brick wall

    Publication Year: 2002, Page(s):576 - 577
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  • Panel: what's the next eda driver?

    Publication Year: 2002, Page(s): 652
    Cited by:  Papers (1)
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  • Coping with buffer delay change due to power and ground noise

    Publication Year: 2002, Page(s):860 - 865
    Cited by:  Papers (23)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (711 KB) | HTML iconHTML

    Variation of power and ground levels affect VLSI circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to predict delays in the presence of uncorrelated power and ground noise. In this paper, we analyze the effect of such noise on signal propagation through a buffer and present s... View full abstract»

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  • Conference author/panelist index

    Publication Year: 2002, Page(s):916 - 919
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  • Osculating Thevenin model for predicting delay and slew of capacitively characterized cells

    Publication Year: 2002, Page(s):866 - 869
    Cited by:  Papers (2)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (410 KB) | HTML iconHTML

    To extrapolate from one point to another using a line, one had better get the slope right. In this paper we apply a similar concept to the important problem in Static Timing Analysis (STA) of predicting cell timing for RC loads using capacitive characterization data. Instead of a line we have a Thevenin circuit, and instead of matching slopes we match load sensitivities. We present a table driven,... View full abstract»

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  • Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control

    Publication Year: 2002, Page(s):854 - 859
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (850 KB) | HTML iconHTML

    This paper addresses the problem of tackling multiple constraints simultaneously during a partitioning driven placement (PDP) process, where a larger solution space is available for constraint-satisfying optimization compared to post-placement methods. A general methodology of multi-constraint satisfaction that balances violation correction and primary optimization is presented. A number of techni... View full abstract»

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  • A solenoidal basis method for efficient inductance extraction

    Publication Year: 2002, Page(s):751 - 756
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (715 KB) | HTML iconHTML

    The ability to compute the parasitic inductance of the interconnect is critical to the timing verification of modern VLSI circuits. A challenging aspect of inductance extraction is the solution of large, dense, complex linear systems of equations via iterative methods. Accelerating the convergence of the iterative method through preconditioning is made difficult due to the non-availability of the ... View full abstract»

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  • A general probabilistic framework for worst case timing analysis

    Publication Year: 2002, Page(s):556 - 561
    Cited by:  Papers (85)  |  Patents (12)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (710 KB) | HTML iconHTML

    The traditional approach to worst-case static-timing analysis is becoming unacceptably conservative due to an ever-increasing number of circuit and process effects. We propose a fundamentally different framework that aims to significantly improve the accuracy of timing predictions through fully probabilistic analysis of gate and path delays. We describe a bottom-up approach for the construction of... View full abstract»

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  • Floorplanning with alignment and performance constraints

    Publication Year: 2002, Page(s):848 - 853
    Cited by:  Papers (17)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (808 KB) | HTML iconHTML

    In this paper, we present a floorplanning algorithm based on sequence pair representation. Our floorplanner has the following important features: (1) It is explicitly designed for fixed-frame floorplanning, which is different from traditional well-researched min-area floorplanning. Moreover, we also show that it can be adapted to minimize total area. (2) It addresses the problem of handling alignm... View full abstract»

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  • Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver

    Publication Year: 2002, Page(s):747 - 750
    Cited by:  Papers (28)  |  Patents (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (508 KB) | HTML iconHTML

    We propose satisfiability checking (SAT) techniques that lead to a consistent performance improvement of up to 3× over state-of-the-art SAT solvers like Chaff on important problem domains in VLSI CAD. We observe that in circuit oriented applications like ATPG and verification, different software engineering techniques are required for the portions of the formula corresponding to learnt claus... View full abstract»

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  • Improving the generality of the fictitious magnetic charge approach to computing inductances in the presence of permeable materials

    Publication Year: 2002, Page(s):552 - 555
    Cited by:  Papers (22)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (438 KB) | HTML iconHTML

    In this paper we present an improvement to the fictitious magnetic charge approach to computing inductances in the presence of permeable materials. The improvement replaces integration over a "non-piercing" surface with a line integral and an efficient quadrature scheme. Eliminating the need to generate non-piercing surfaces substantially simplifies handling problems with general geometries of per... View full abstract»

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  • TCG-S: orthogonal coupling of P*-admissible representations for general floorplans

    Publication Year: 2002, Page(s):842 - 847
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (845 KB) | HTML iconHTML

    Extends the concept of the P-admissible floorplan representation to that of the P*-admissible one. A P*-admissible representation can model the most general floorplans. Each of the currently existing P*-admissible representations, SP, BSG, and TCG, has its strengths as well as weaknesses. We show the equivalence of the two most promising P*-admissible representations, TCG and SP, and integrate TCG... View full abstract»

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  • Combined BEM/FEM substrate resistance modeling

    Publication Year: 2002, Page(s):771 - 776
    Cited by:  Papers (12)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (613 KB) | HTML iconHTML

    For present-day microelectronic designs, it is becoming ever more important to accurately model substrate coupling effects. Basically, either a Finite Element Method (FEM) or a Boundary Elements Method (BEM) can be used. The FEM is the most versatile and flexible whereas the BEM is faster, but requires a stratified, layout-independent doping profile for the substrate. Thus, the BEM is unable to pr... View full abstract»

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  • SAT with partial clauses and back-leaps

    Publication Year: 2002, Page(s):743 - 746
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (442 KB) | HTML iconHTML

    This paper presents four new powerful SAT optimization techniques: partial clauses, back-leaps, immediate implications, and local decisions. These optimization techniques can be combined with SAT mechanisms used in Chaff, SATO, and GRASP to develop a new solver that significantly outperforms its predecessors on a large set of benchmarks. Performance improvements for standard benchmark groups vary ... View full abstract»

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  • Regularization of hierarchical VHDL-AMS models using bipartite graphs

    Publication Year: 2002, Page(s):548 - 551
    Cited by:  Papers (2)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (541 KB) | HTML iconHTML

    The powerful capability of VHDL-AMS to describe complex continuous systems in form of differential algebraic equations (DAEs) often leads to problems during numerical simulation. This paper presents a discrete algorithm to analyze unsolvable DAE systems and to correct the underlying hierarchical VHDL-AMS description automatically in interaction with the designer, avoiding time-consuming manual err... View full abstract»

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  • CMOS: a paradigm for low power wireless?

    Publication Year: 2002, Page(s):836 - 841
    Cited by:  Papers (5)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (620 KB) | HTML iconHTML

    An overview and comparison of different topologies for wireless architectures are discussed, where the main focus lies on the power consumption and possibilities towards integration and reduction of external components. Architectures with reduced number of building blocks (both internal and external) are presented where the main benefits are the low costs, both in the CMOS technology as well as th... View full abstract»

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  • Model composition for scheduling analysis in platform design

    Publication Year: 2002, Page(s):287 - 292
    Cited by:  Papers (14)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (836 KB)

    We present a compositional approach to analyze timing behavior of complex platforms with different scheduling strategies. The approach uses event interfacing in order to couple previously incompatible analysis techniques which provide subsystem and component behavior. Based on these interfaces, event propagation using abstract models is used to derive global system timing properties. View full abstract»

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  • Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems

    Publication Year: 2002, Page(s):405 - 410
    Cited by:  Papers (13)  |  Patents (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (872 KB) | HTML iconHTML

    Several approaches have been proposed for the syntax-directed compilation of asynchronous circuits from high-level specification languages, such as Balsa and Tangram. Both compilers have been successfully used in large real-world applications; however, in practice, these methods suffer from significant performance overheads due to their reliance on straightforward syntax-directed translation. This... View full abstract»

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  • Effective diagnostics through interval unloads in a BIST environment

    Publication Year: 2002, Page(s):249 - 254
    Cited by:  Papers (24)  |  Patents (9)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (682 KB) | HTML iconHTML

    Logic built-in self test (BIST) is increasingly being adopted to improve test quality and reduce test costs for rapidly growing designs. Compared to deterministic automated test pattern generation (ATPG), BIST presents inherent fault diagnostic challenges. Previous diagnostic techniques have been limited in their diagnosis resolution and/or require significant hardware overhead. This paper propose... View full abstract»

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