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Multiple-Valued Logic, 2002. ISMVL 2002. Proceedings 32nd IEEE International Symposium on

Date 15-18 May 2002

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  • Proceedings 32nd IEEE International Symposium on Multiple-Valued Logic [front matter]

    Publication Year: 2002
    Save to Project icon | Request Permissions | PDF file iconPDF (346 KB)  
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  • Author index

    Publication Year: 2002 , Page(s): 289
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    Freely Available from IEEE
  • Partial hyperclones on a finite set

    Publication Year: 2002 , Page(s): 17 - 22
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (329 KB) |  | HTML iconHTML  

    The composition-closed sets of partial multi-valued operations, called partial hyperclones, defined on the finite set E(k)={0, 1, ..., k-1} (k⩾2) are investigated. It is shown that the lattice of all partial hyperclones is dually atomic and has only a finite number of dual atoms (maximal partial hyperclones). Some of them are presented in this paper. The full list of maximal restriction-closed... View full abstract»

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  • Logic for static hazard detection of multiple-valued logic circuits with TSUM, MIN, and Literals

    Publication Year: 2002 , Page(s): 46 - 51
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (291 KB) |  | HTML iconHTML  

    Multiple-valued logic circuits are often implemented by the current mode CMOS technology, or sometimes the voltage mode technology. Even if multiple-valued logic circuits are realized by either one of the two technologies, the signal propagation delay will cause hazards pluses, which are undesirable short pulses in circuits. This paper will focus on static hazards in multiple-valued logic circuits... View full abstract»

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  • A conjunctive canonical expansion of multiple-valued functions

    Publication Year: 2002 , Page(s): 35 - 38
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (251 KB) |  | HTML iconHTML  

    A generalization of McMillan's conjunctive expansion of Boolean functions to the case of multiple-valued input binary-valued output functions is presented. It is based on the operation of generalized cofactor, defined by employing a new distance measure on truth assignments, called m-valued weighted distance. Using our result, Boolean multiple-output functions can be expanded directly by treating ... View full abstract»

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  • On functions defined on free Boolean algebras

    Publication Year: 2002 , Page(s): 192 - 199
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (323 KB) |  | HTML iconHTML  

    We characterize measures on free Boolean algebras and we examine the relationships that exists between measures and binary tables in relational databases. It is shown that these measures are completely defined by their values on positive conjunctions and an algorithm that leads to the construction of measures starting from its values on a positive conjunction is also given, including a formula tha... View full abstract»

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  • The word-level models for efficient computation of multiple-valued functions.2. LWL based model

    Publication Year: 2002 , Page(s): 209 - 215
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (564 KB) |  | HTML iconHTML  

    For pt.1 see ibid., p. 202-8 (2002). This paper is a continuation of the study of neural-like networks (NLNs) for computation of multiple-valued logic (MVL) functions. NLN is defined as a feedforward network with no learning. In contrast to classical neural networks with threshold gates (TGs), the proposed NLN is built of so-called neuron-like gates (NLGs). It was shown in our previous study that ... View full abstract»

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  • Chrestenson spectrum computation using Cayley color graphs

    Publication Year: 2002 , Page(s): 123 - 128
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (358 KB) |  | HTML iconHTML  

    A method based on eigenvalue computations is formulated for computing the Chrestenson spectrum of a discrete p-valued function. This technique is developed by considering an extension to the sate approach of computation of the Walsh spectrum for a two-valued function and is then generalized to the p-valued case. Algebraic groups are formulated that correspond to Cayley color graphs based on the fu... View full abstract»

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  • Efficient calculation of fixed-polarity polynomial expressions for multiple-valued logic functions

    Publication Year: 2002 , Page(s): 76 - 82
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (300 KB) |  | HTML iconHTML  

    This paper presents a tabular technique for the calculation of fixed-polarity polynomial expressions for multiple-valued (MV) functions. The technique is derived from a generalization of the corresponding methods for fixed-polarity Reed-Muller (FPRM) expressions for switching functions. All useful features of tabular techniques for FPRMs (e.g. simplicity of the involved operations and high possibi... View full abstract»

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  • Some results on the centralizers of monoids in clone theory

    Publication Year: 2002 , Page(s): 10 - 16
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (448 KB)  

    For a set S of multi-variable operations on a k-element set, the centralizer S' is the set of operations which commute with all operations in S. In this paper we concentrate on monoids of unary operations and centralizers of such monoids. In the course of discussion the Kuznetsov criterion is effectively used. First we study such monoids whose centralizer is the trivial (least) clone Jk... View full abstract»

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  • Sierpinski gaskets for logic functions representation

    Publication Year: 2002 , Page(s): 39 - 45
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (414 KB) |  | HTML iconHTML  

    This paper introduces a new approach to represent logic functions in the form of Sierpinski gaskets. The structure of the gasket allows it to be manipulated with the corresponding logic expression using the recursive essence of fractals. Thus, the Sierpinski gasket's pattern has myriad useful properties which can enhance the practical features of other graphic representations like decision diagram... View full abstract»

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  • The role of super-fast transforms in speeding up quantum computations

    Publication Year: 2002 , Page(s): 129 - 135
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (260 KB) |  | HTML iconHTML  

    We present the role that spectral methods play in the development of the most impressive quantum algorithms, such as the polynomial time number factoring algorithm by Shor. While the fast transform algorithms reduce the number of operations needed in obtaining the transforms from O(22n) to O(n2n), quantum transforms are in comparison super-fast. The quantum Fourier transform ... View full abstract»

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  • The word-level models for efficient computation of multiple-valued functions I. LAR based model

    Publication Year: 2002 , Page(s): 202 - 208
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (555 KB) |  | HTML iconHTML  

    A new model of a multi-level combinational multiple-valued logic (MVL) circuit with no feedback and no learning is introduced. This model includes neuron-like gates (NLGs), each represents a level of the MVL circuit, so that the number of NLGs in the corresponding neural-like network (NLN) is equal to the number of levels in the circuit. The formal description of an NLG is a linear arithmetic expr... View full abstract»

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  • Multiple-valued data recovery techniques for band-limited channels in VLSI

    Publication Year: 2002 , Page(s): 54 - 60
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (823 KB) |  | HTML iconHTML  

    Increasing VLSI system performance requires higher bus bandwidths while maintaining low cost in area, power and complexity. Bus bandwidth improvement is historically achieved by increased clock frequency, but is restricted by a signal deterioration due to intersymbol interference (ISI). Although the use of a multi-level signal can increase signaling bandwidth without increasing clock frequency, IS... View full abstract»

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  • Design of dynamic reliability indices

    Publication Year: 2002 , Page(s): 144 - 148
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (279 KB)  

    The multi-state system reliability is investigated in this paper. The new class of reliability indices is obtained. We have called these indices as dynamic reliability indices. These indices estimate influence upon the multi-state system reliability by the capacity levels of a system component. The multiple-valued logic mathematical tools are used for calculation of dynamic reliability indices View full abstract»

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  • Multiple-valued-digit number representations in arithmetic circuit algorithms

    Publication Year: 2002 , Page(s): 224 - 235
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (332 KB) |  | HTML iconHTML  

    Multiple-valued-digit number representations, i.e., positional weighted number representations with a digit set consisting of more than two values, are often used in arithmetic circuit algorithms for high-speed and/or area efficient computation. These algorithms may be implemented by a multiple-valued logic more efficiently than by the binary logic. This article shows how these number representati... View full abstract»

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  • Some remarks on linear transform of variables in representation of adders by word-level expressions and spectral transform decision diagrams

    Publication Year: 2002 , Page(s): 116 - 122
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (300 KB) |  | HTML iconHTML  

    Discusses transforms for the reduction of complexity of different representations for binary adders described by binary-valued multiple-output functions and integer-valued single-output functions. For these bit-level and word-level representations of adders, we compare the complexity of the corresponding polynomial expressions and related decision diagrams. We discuss a linear transform of input v... View full abstract»

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  • Design and implementation of error detection and correction circuitry for multilevel memory protection

    Publication Year: 2002 , Page(s): 89 - 95
    Cited by:  Papers (3)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (315 KB) |  | HTML iconHTML  

    Traditional memories use only two levels per cell (0/1), which limits their storage capacity to 1 bit per cell. By doubling the cell capacity, we increase the density of the memory at the expense of its reliability. There are several types of memories that employ multi-level techniques. The subject of this paper is the design of a multi-level dynamic random access memory (MLDRAM). The problem of i... View full abstract»

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  • Multiple-valued logic-in-memory VLSI based on ferroelectric capacitor storage and charge addition

    Publication Year: 2002 , Page(s): 161 - 166
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1031 KB)  

    A multiple-valued logic-in-memory VLSI using ferroelectric capacitors is proposed to realize an arithmetic-oriented VLSI with real-time programmable capacitor storage. The use of a remnant-polarization charge on a ferroelectric capacitor makes it possible to perform not only a real-time programmable storage function but also a linear-sum function, thereby resulting in a compact hardware while main... View full abstract»

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  • Evaluation of static variable ordering heuristics for MDD construction [multi-valued decision diagrams]

    Publication Year: 2002 , Page(s): 254 - 260
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (377 KB) |  | HTML iconHTML  

    After designing a multi-valued logic network (MVLN), the resulting circuit has to be verified to guarantee its functional correctness. The most promising technique to cope with increasing device size is formal methods. Ordered multi-valued decision diagrams (OMDDs) have been proposed for formal verification of MVLNs. But OMDDs are very sensitive to the chosen variable ordering, and several orderin... View full abstract»

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  • Comparison of different features of quaternary Reed-Muller canonical forms and some new statistical results

    Publication Year: 2002 , Page(s): 83 - 88
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (239 KB) |  | HTML iconHTML  

    An integrated set of utility programs in C is presented. These can be used to perform calculations in any quaternary Reed-Muller algebra by entering addition and multiplication tables, and the zero-polarity transform matrix. For every completely specified quaternary function, canonical forms are generated for any pre-selected set of polarities. A laboratory is used to generate statistics comparing... View full abstract»

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  • Improving the characterization of p-valued threshold functions

    Publication Year: 2002 , Page(s): 28 - 34
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (277 KB) |  | HTML iconHTML  

    Renewed interest in multiple-valued threshold logic in recent years, from the point of view of neural networks, motivates the return to deepen research on multiple-valued threshold logic. Realizations of threshold logic are based on a partition of the set of multiple-valued functions of a given arity and tables of characterizing parameters of each block of the equivalence relation. Any improvement... View full abstract»

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  • Independence of each axiom in a set of axioms and complete sets of axioms of Boolean algebra

    Publication Year: 2002 , Page(s): 185 - 191
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (250 KB) |  | HTML iconHTML  

    We investigate fundamental properties of axioms of Boolean algebra in detail by using the Method of Indeterminate Coefficients. Three axioms, one of the complementary laws, one of the distributive laws and one of the least element (a), greatest element (b) and the absorption laws are essential for the algebra because those are independent from all other axioms of Boolean algebra. Then we research ... View full abstract»

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  • Voltage comparator circuits for multiple-valued CMOS logic

    Publication Year: 2002 , Page(s): 67 - 73
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (319 KB) |  | HTML iconHTML  

    A new voltage-mode comparator circuit for use in CMOS multiple-valued logic circuits is introduced. Existing comparator circuits for this application use static current or clocking and thus consume static power or clocking power. In order to reduce these power requirements, we have examined static circuit designs that eliminate DC current paths when the inputs and outputs are at logical values. El... View full abstract»

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  • Equations in the algebra of logic

    Publication Year: 2002 , Page(s): 2 - 8
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (282 KB) |  | HTML iconHTML  

    We survey the basic results in the theory of Boolean equations and the theory of equations in Post algebras. The two theories share four common features, which are analysed from the point of view of universal algebra; this yields further generalizations. Applications include a revision of Arystoteles' syllogistics and the study of Boolean analogues of modus ponens and the deduction theorem View full abstract»

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