27th ACM/IEEE Design Automation Conference

24-28 June 1990

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  • 27th ACM/IEEE Design Automation Conference. Proceedings 1990 (Cat. No.90CH2894-4)

    Publication Year: 1990
    Request permission for commercial reuse | PDF file iconPDF (25 KB)
    Freely Available from IEEE
  • LECSIM: a levelized event-driven compiled logic simulator

    Publication Year: 1990, Page(s):491 - 496
    Cited by:  Papers (30)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    LECSIM is an efficient logic simulator which integrates the advantages of event-drive interpretive simulation and levelized compiled simulation. Two techniques contribute to the high efficiency. First, it employs the zero-delay simulation model with levelized event scheduling to eliminate most unnecessary evaluations. Second, it compiles the central event scheduler into simple local scheduling seg... View full abstract»

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  • Comparing structurally different views of a VLSI design

    Publication Year: 1990, Page(s):200 - 206
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    In large VLSI design projects, it is desirable to compare alternate views that use different hierarchies. However, existing techniques either require essentially identical hierarchies (which is sometimes an unacceptable restriction) or must flatten to remove the differences (which may be very costly). A new technique, informed comparison, has neither of these shortcomings. First, hierarchy transfo... View full abstract»

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  • Analysis and design of latch-controlled synchronous digital circuits

    Publication Year: 1990, Page(s):111 - 117
    Cited by:  Papers (34)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    A new formulation of the timing constraintss for latch-controlled synchronous digital circuits is presented. The authors show that the constraints are mildly nonlinear, and prove the equivalence of the nonlinear optimal cycle time calculation problem to an associated and simpler linear programming (LP) problem. An LP-based algorithm is presented which is guaranteed to obtain the optimal cycle time... View full abstract»

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  • Distributed and parallel demand driven logic simulation

    Publication Year: 1990, Page(s):485 - 490
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    Based on a demand-driven approach, distributed and parallel simulation algorithms are proposed. Demand-driven simulation tries to minimize a number of component computations by performing only those required for the watched output requests. For a specific output value request the required input line values are requested from the related component. The authors present a distributed demand-driven al... View full abstract»

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  • Design methodology management-a CAD framework initiative perspective

    Publication Year: 1990, Page(s):278 - 283
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    The design of today's electronic systems involves the use of a growing number of complex CAD tools. Invoking and controlling these tools, independently or as part of a captured, multioperation flow, remains an error-prone and largely unsolved problem. This problem is the focus of the design methodology management technical subcommittee (DMMTSC) of the CAD framework initiative. The authors describe... View full abstract»

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  • Pad placement and ring routing for custom chip layout

    Publication Year: 1990, Page(s):193 - 199
    Cited by:  Papers (7)  |  Patents (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    An optimum scheme is presented for interconnecting the chip core and the I/O pads in the final stage of physical design. The pad placement routing, based on linear assignment, determines the dimension of the pad ring and selects the optimum position for each pad with the objective of minimizing the chip area and the total wire length. The router is based on a channel-routing algorithm which incorp... View full abstract»

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  • Parallel circuit simulation using hierarchical relaxation

    Publication Year: 1990, Page(s):394 - 399
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    Described is a class of parallel algorithms for circuit simulation based on hierarchical relaxation that has been implemented on the Cedar multiprocessor. The Cedar machine is a reconfigurable, general-purpose supercomputer that was designed and implemented at the University of Illinois. A hierarchical circuit simulation scheme is developed to exploit the hierarchical organization of Cedar. The ne... View full abstract»

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  • MHERTZ: a new optimization algorithm for floorplanning and global routing

    Publication Year: 1990, Page(s):107 - 110
    Cited by:  Papers (5)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    Timing-driven placement is essential for full-custom VLSI, gallium arsenide, and ECL circuits to meet wire timing constraints. A new macro/custom cell floorplanner and global router, called MHERTZ, is described. It meets wire timing constraints by using force-directed cost functions in multistart and simulated annealing (SA) optimization algorithms. MHERTZ also prevents wire coupling, meets specif... View full abstract»

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  • Techniques for unit-delay compiled simulation

    Publication Year: 1990, Page(s):480 - 484
    Cited by:  Papers (18)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    Two techniques for compiled unit-delay simulation have been presented. These are a PC-set (the set of potential change times) method and a parallel technique. The PC-set method analyzes a network, determines a set of potential change times for each net, and generates gate simulations for each potential change. The parallel technique, which is based on a concept of parallel fault simulation, is fas... View full abstract»

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  • Brel-a PROLOG knowledge-based system shell for VLSI CAD

    Publication Year: 1990, Page(s):272 - 277
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    A knowledge-based system (KBS) shell, called Brel, for VLSI CAD systems is described. Brel has a context recovery system that implements memorization and forgetting and supports a wide range of knowledge representation (frames, rules, procedures, first-order logic, etc.) Brel was developed using PROLOG and successfully used to implement PIAF, a top-down floorplanning system, and TEMPO, a formal ve... View full abstract»

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  • A hardware implementation of gridless routing based on content addressable memory

    Publication Year: 1990, Page(s):646 - 649
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    A new gridless router accelerated by content addressable memory (CAM) is presented. A gridless version of the line-expansion algorithm is implemented, which always finds a path if one exists. The router runs in linear time by means of the CAM-based accelerator. Experimental results show that the more obstacles there are in the routing region, the more effective the CAM-based approach is. The CAM-b... View full abstract»

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  • An object-oriented VHDL design environment

    Publication Year: 1990, Page(s):431 - 436
    Cited by:  Papers (13)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    A system-level design environment (SDE) for the VHSIC hardware description language (VHDL) is presented. The object-oriented approach is used for modeling the VHDL entities, design constraints, and even design patterns. The data model and its internal schema, which are suitable for the VHDL semantics, are proposed. SDE allows a designer to reconfigure the designed schematic by binding its generic ... View full abstract»

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  • An analytical approach to floorplan design and optimization

    Publication Year: 1990, Page(s):187 - 192
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    An analytical method for VLSI general floorplan design and optimization is proposed. This method is based on a mixed integer programming model and all application of a standard mathematical software. The method allows arbitrary combinations of rigid and flexible modules. Various objective functions, such as chip area, interconnection length, timing delays or any combinations of them, are permitted... View full abstract»

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  • Data path tradeoffs using MABAL

    Publication Year: 1990, Page(s):511 - 516
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    A set of novel tradeoff experiments using MABAL, a module and bus allocation program, is described. MABAL uses a simple heuristic algorithm to concurrently perform functional unit allocation, register allocation, interconnect allocation, and module binding, while minimizing overall cost. MABAL was used to produce over 3000-RTL (register transfer level) designs from a specification which had been p... View full abstract»

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  • Synthesis and optimization procedures for robustly delay-fault testable combinational logic circuits

    Publication Year: 1990, Page(s):221 - 227
    Cited by:  Papers (38)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (768 KB)

    Recently developed necessary and sufficient conditions for robust path-delay-fault testability are applied to develop synthesis procedures which produce two-level and multilevel circuits with high degrees of robust path delay fault testability. For circuits which can be flattened to two levels, a covering procedure is given which optimizes for robust path delay fault testability. These two-level c... View full abstract»

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  • Datapath generator based on gate-level symbolic layout

    Publication Year: 1990, Page(s):388 - 393
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    A data-path generator that generates high-density LSI mask layouts equivalent to hand-crafted ones is described. An entry of the generator is a hierarchical symbolic layout at the gate level. The bit-and-row-slicing technique is a key feature for realizing large-size and high-density data-path generation. A 21 K-transistor data-path whose density is 5.64 KTr/mm2, greater than the 5.38 K... View full abstract»

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  • Corolla based circuit partitioning and resynthesis

    Publication Year: 1990, Page(s):607 - 612
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    Application of corolla-based partitioning to improve synthesis of large multi-level logic circuits is introduced. First, stem regions, petals, and corollas are defined. Next, the partitioning algorithm is outlined and the resynthesis process is described. Results of partitioning and logic resynthesis on a variety of large circuit benchmarks are summarized. It is found that logic resynthesis based ... View full abstract»

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  • Performance-driven constructive placement

    Publication Year: 1990, Page(s):103 - 106
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    A new approach to performance-driven placement based on a window concept is presented. Timing constraints are first converted to geometric shapes using the defined windows. A window represents a region in which all the modules along a given path can be placed without degrading the circuit performance. Then a constructive placement process uses the window information to select an unplaced module, a... View full abstract»

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  • The influences of fault type and topology on fault model performance and the implications to test and testable design

    Publication Year: 1990, Page(s):673 - 678
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    A new method, difference propagation, is proposed to analyze fault models in combinational circuits. It propagates Boolean functional information represented by ordered binary decision diagrams. Results are presented concerning exact detectabilities and syndromes for a set of benchmark circuits. The data suggest answers to open questions in CAD and represent the first data of this type for bridgin... View full abstract»

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  • LiB: a cell layout generator

    Publication Year: 1990, Page(s):474 - 479
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    An automatic layout generation system, called LiB, for the library cells used in CMOS ASIC design is presented. LiB takes a transistor-level circuit schematic in SPICE format and outputs a symbolic layout. In LiB, the intra-cell routing runs not only between PMOS and NMOS but also on diffusion islands as well as the two side regions (one between the PMOS diffusion and the power line, and the other... View full abstract»

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  • SKILL: a CAD system extension language

    Publication Year: 1990, Page(s):266 - 271
    Cited by:  Papers (7)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    SKILL is a programming language that supports both command entry and procedural customization in the Opus design framework. The author examines the requirements that motivate the provision of a programming language available to the user and describes some of the technical characteristics of the language design and implementation. Experience with the language is described and a number of programmin... View full abstract»

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  • Layout compaction with attractive and repulsive constraints

    Publication Year: 1990, Page(s):369 - 374
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    A one-dimensional VLSI layout compaction algorithm with attractive and repulsive constraints is proposed. Depending on these constraints, the proposed algorithm shrinks [expands] the spaces among the specified layout elements without causing any design rule violations. The resultant layout has less cross-talks and delay. The proposed network simplex algorithm experimentally proves to be efficient ... View full abstract»

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  • Behavioral fault simulation in VHDL

    Publication Year: 1990, Page(s):587 - 593
    Cited by:  Papers (26)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    Two tools which facilitate a fault simulation of behavioral models described using the VHSIC hardware description language (VHDL) are presented. The first tool is the behavioral fault mapper (BFM). The BFM algorithm accepts a fault-free VHDL model and a fault-list of N faults from which it produces N faulty models. The process of mapping the faults in the fault-list onto copies o... View full abstract»

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  • New placement and global routing algorithms for standard cell layouts

    Publication Year: 1990, Page(s):642 - 645
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    The placement algorithm, called the hierarchical clustering with min-cut exchange (HCME), is effective at avoiding being trapped in local optimum solutions. The global routing algorithm does not route the nets one by one and therefore the results are independent of the net order and channel order. In this algorithm, channel width is minimized under a cost function, in which the trade-off between t... View full abstract»

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