By Topic

2016 Formal Methods in Computer-Aided Design (FMCAD)

3-6 Oct. 2016

Filter Results

Displaying Results 1 - 25 of 39
  • [Front cover]

    Publication Year: 2016, Page(s): 1
    Request permission for commercial reuse | PDF file iconPDF (194 KB)
    Freely Available from IEEE
  • [Copyright notice]

    Publication Year: 2016, Page(s): 1
    Request permission for commercial reuse | PDF file iconPDF (31 KB)
    Freely Available from IEEE
  • Preface

    Publication Year: 2016, Page(s):1 - 2
    Request permission for commercial reuse | PDF file iconPDF (23 KB) | HTML iconHTML
    Freely Available from IEEE
  • Organization committee

    Publication Year: 2016, Page(s): 1
    Request permission for commercial reuse | PDF file iconPDF (30 KB)
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2016, Page(s):1 - 2
    Request permission for commercial reuse | PDF file iconPDF (30 KB)
    Freely Available from IEEE
  • Formal verification for computer security: Lessons learned and future directions

    Publication Year: 2016, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (43 KB)

    Formal verification techniques have been fruitful for a broad spectrum of different security applications and domains. However, many important questions and considerations influence the success of applying formal verification techniques to security applications and domains. In this talk, I will share lessons learned from experience of over a decade in applying formal verification techniques to sec... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Understanding evolution through algorithms

    Publication Year: 2016, Page(s): 2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (43 KB)

    Why is evolution so successful? What is the role of sex (recombination)? Why is there so much diversity in populations? How do novel traits arise? Are mutations random? And is evolution optimizing something? This talk will review recent work by the speaker and collaborators aiming at understanding the many persistent mysteries of evolution through computational ideas. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Network verification — When Clarke meets Cerf

    Publication Year: 2016, Page(s): 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (44 KB)

    Surveys reveal that network outages are prevalent, and that many outages take hours to resolve, resulting in significant lost revenue. Many bugs are caused by errors in configuration files which are programmed using arcane, low-level languages, akin to machine code. Taking our cue from program and hardware verification, we suggest fresh approaches. I will first describe a geometric model of networ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Machine learning and systems for the next frontier in formal verification

    Publication Year: 2016, Page(s): 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (42 KB) | HTML iconHTML

    Summary form only given. This tutorial covers basics of machine learning, systems and infrastructure considerations for performing machine learning at scale, and applications of machine learning to improve formal verification performance and usability. It starts with blackbox classifier training with gradient descent, and proceeds on to deep network training and simple convolutional neural network... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Verifying hyperproperties of hardware systems

    Publication Year: 2016, Page(s): 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (48 KB) | HTML iconHTML

    This tutorial presents hardware verification techniques for hyperproperties. The most prominent application of hyperproperties is information flow security: information flow policies characterize the secrecy and integrity of a system by comparing two or more execution traces, for example by comparing the observations made by an external observer on execution traces that result from different value... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A paradigm shift in verification methodology

    Publication Year: 2016, Page(s): 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (44 KB) | HTML iconHTML

    Todays SoCs are driving unprecedented verification complexity. The combination of billions of gates, system-level functionality on a chip, complex design methodologies like asynchronous clock domains and an explosion of untimed paths on a chip, interacting dynamic power domains, aggressive reset schemes etcetera could have been the perfect storm to staunch productivity. Instead it has turned out t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Program synthesis for networks

    Publication Year: 2016, Page(s): 7
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (43 KB) | HTML iconHTML

    Software is eating the world. But how will we write all the programs to control everything from sensors to data centers? Program synthesis provides an answer. It increases the productivity of programmers by enabling them to capture their insights in a variety of forms, not just in standard code. In this tutorial, we focus on some challenges in programming networks, and we show how program synthesi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The FMCAD 2016 graduate student forum

    Publication Year: 2016, Page(s): 8
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (57 KB) | HTML iconHTML

    The FMCAD Student Forum provides a platform for graduate students at any career stage to introduce their research to the wider Formal Methods community, and solicit feedback. In 2016, the event took place in Mountain View, California, as integral part of the FMCAD conference. Ten students were invited to give a short talk and present a poster illustrating their work. The presentations covered a br... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Soundness of the quasi-synchronous abstraction

    Publication Year: 2016, Page(s):9 - 16
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB) | HTML iconHTML

    Many critical real-time embedded systems are implemented as a set of processes that execute periodically with bounded jitter and communicate with bounded transmission delay. The quasi-synchronous abstraction was introduced by P. Caspi for model-checking the safety properties of applications running on such systems. The simplicity of the abstraction is appealing: the only events are process activat... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Synthesizing adaptive test strategies from temporal logic specifications

    Publication Year: 2016, Page(s):17 - 24
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (237 KB) | HTML iconHTML

    Constructing good test cases is difficult and time-consuming, especially if the system under test is still under development and its exact behavior is not yet fixed. We propose a new approach to compute test cases for reactive systems from a given temporal logic specification. The tests are guaranteed to reveal certain simple bugs (like occasional bit-flips) in every realization of the specificati... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening

    Publication Year: 2016, Page(s):25 - 32
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (223 KB) | HTML iconHTML

    We address the problem of reducing the size of Craig interpolants used in SAT-based Model Checking. Craig interpolants are AND-OR circuits, generated by post-processing refutation proofs of SAT solvers. Whereas it is well known that interpolants are highly redundant, their compaction is typically tackled by reducing the proof graph and/or by exploiting standard logic synthesis techniques. Furtherm... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Extracting behaviour from an executable instruction set model

    Publication Year: 2016, Page(s):33 - 40
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (150 KB) | HTML iconHTML

    Presenting large formal instruction set models as executable functions makes them accessible to engineers and useful for less formal purposes such as simulation. However, it is more difficult to extract information about the behaviour of individual instructions for reasoning. We present a method which combines symbolic evaluation and symbolic execution techniques to provide a rule-based view of in... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Categorical semantics of digital circuits

    Publication Year: 2016, Page(s):41 - 48
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (761 KB) | HTML iconHTML

    This paper proposes a categorical theory of digital circuits based on monoidal categories and graph rewriting. The main goal of this paper is conceptual: to fill a foundational gap in reasoning about digital circuits, which is currently almost exclusively semantic (simulations). The level of abstraction we target is circuits with discrete signal levels, discrete time, and explicit delays, which is... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Equivalence checking by logic relaxation

    Publication Year: 2016, Page(s):49 - 56
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB) | HTML iconHTML

    We introduce a new framework for Equivalence Checking (EC) of Boolean circuits based on a general technique called Logic Relaxation (LoR). LoR is meant for checking if a propositional formula G has only “good” satisfying assignments specified by a design property. The essence of LoR is to relax G into a formula Grlx and compute a set S that contains all assignments that sa... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Minimal unsatisfiable core extraction for SMT

    Publication Year: 2016, Page(s):57 - 64
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB) | HTML iconHTML

    Finding a minimal (i.e., irreducible) unsatisfiable core (MUC), and high-level minimal unsatisfiable core (also known as group MUC, or GMUC), are well-studied problems in the domain of propositional satisfiability. In contrast, in the domain of SMT, no solver in the public domain produces a minimal or group-minimal core. Several SMT solvers, like Z3, produce a core but do not attempt to minimize i... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient uninterpreted function abstraction and refinement for word-level model checking

    Publication Year: 2016, Page(s):65 - 72
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (737 KB) | HTML iconHTML

    Methods for word-level model checking based on purely bit-level techniques have difficulties with heavy arithmetic logic. Word-level and SMT approaches often are limited by relying on (incomplete) bounded model checking. UFAR, a hybrid word- and bit-level approach, addresses these issues, taking advantage of modern bit-level sequential techniques while heavy arithmetic logic is addressed by word-l... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimizing horn solvers for network repair

    Publication Year: 2016, Page(s):73 - 80
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB)

    Automatic program repair modifies a faulty program to make it correct with respect to a specification. Previous approaches have typically been restricted to specific programming languages and a fixed set of syntactical mutation techniques-e.g., changing the conditions of if statements. We present a more general technique based on repairing sets of unsolvable Horn clauses. Working with Horn clauses... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On ∃ ∀ ∃! solving: A case study on automated synthesis of magic card tricks

    Publication Year: 2016, Page(s):81 - 84
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (125 KB) | HTML iconHTML

    In formal synthesis, the goal is to find a composition of components from a finite library such that the composition satisfies a given logical specification. In this paper, we consider the problem of synthesizing magic card tricks from component actions, where some of the actions depend on non-deterministic choices made by the audience. This problem can be naturally represented as a quantified log... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Property-directed k-induction

    Publication Year: 2016, Page(s):85 - 92
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (202 KB) | HTML iconHTML

    IC3 and k-induction are commonly used in automated analysis of infinite-state systems. We present a reformulation of IC3 that separates reachability checking from induction reasoning. This makes the algorithm more modular, and allows us to integrate IC3 and k-induction. We call this new method property-directed k-induction (PD-KIND). We show that k-induction is more powerful than regular induction... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Lazy proofs for DPLL(T)-based SMT solvers

    Publication Year: 2016, Page(s):93 - 100
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (249 KB) | HTML iconHTML

    With the integration of SMT solvers into analysis frameworks aimed at ensuring a system's end-to-end correctness, having a high level of confidence in these solvers' results has become crucial. For unsatisfiable queries, a reasonable approach is to have the solver return an independently checkable proof of unsatisfiability. We propose a lazy, extensible and robust method for enhancing DPLL(T)-styl... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.