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Devices, Circuits and Systems, 2002. Proceedings of the Fourth IEEE International Caracas Conference on

Date 19-19 April 2002

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Displaying Results 1 - 25 of 103
  • Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)

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  • VDDQ: a built-in self-test scheme for analog on-chip diagnosis, compliant with the IEEE 1149.4 mixed-signal test bus standard

    Page(s): I026
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    An innovative self-diagnostic method called VDDQ is presented. The proposed method is compliant with the IEEE 1149.4 mixed-signal test bus standard. It performs a pass or fail function of the analog circuit. The VDDQ method sequentially senses the quiescent voltage of several nodes on the circuit under test (CUT) and compares them with their nominal value. The method produces a 10 bit digital vector, with nodal information including a pass or fail flag, plus the analog voltage sensed. Simulation results are provided for the flag and amplifier circuit used for the design of the testing circuit. Through simulations, this testing scheme has performed a test per node every millisecond. This will potentially allow a defect free IC to enter the market in significantly less time than with conventional testing methods. View full abstract»

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  • Author addresses

    Page(s): 567 - 584
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  • Author's index

    Page(s): 585 - 586
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  • Recent advances in transport modeling for miniaturized CMOS devices

    Page(s): D027-1 - D027-8
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    With the rapid feature size reduction of modern semiconductor devices accurate description of hot-carrier phenomena is becoming very important. Frequently used carrier transport models are the traditional drift-diffusion model and energy-transport models which also consider the average carrier energy as an independent solution variable. Recent results show, however, that the average energy is in many cases not sufficient for accurate modeling. Both the transport models themselves and the models for the physical parameters seem to be affected. After a review of the conventional models we present highly accurate impact ionization and gate current models based on a six moments transport model. View full abstract»

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  • The statistical properties of light generated by circular-grating distributed Bragg reflector laser with integrated outcoupler

    Page(s): D028-1 - D028-8
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    We analyze the influence of integrated outcoupler, characterized by effective end-reflectivity, on the statistical properties of light generated by circular-grating distributed Bragg reflector laser. In our paper we concentrate on the effects resulting from the nonorthogonality properties of laser modes. The semi classical approach based on stationary and time-dependent solution of the Fokker-Planck equation is used. Numerical results obtained for CG-DBR structure reveal the behavior of statistical parameters of light such as the mean laser intensity, intensity fluctuations and the laser linewidth as a functions of the effective complex reflection of the integrated outcoupler. View full abstract»

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  • Optimal design of high output power class E amplifier

    Page(s): P012-1 - P012-5
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    A novel push-pull amplifier based on class E configuration is proposed. The output power of this new structure is four times of that of the conventional single end class E amplifier with same supply voltage. Detailed analysis and design procedures, with a design example, are also given in this paper. View full abstract»

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  • CMOS analog sine function generator using lateral-PNP bipolar transistors

    Page(s): C030 - C1-4
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    An implementation in CMOS technology of the ingenious analog sine function generator invented by Barrie Gilbert over two decades ago (Electron. Lett., vol. 13, pp. 506-508, 1977) is described in this paper. New in this circuit is the use of lateral-PNP bipolar transistors to build the core of the sine generator together with MOS transistors in the saturation region making up the rest of the circuit. Experimental results from prototypes of the circuit fabricated in 0.8 μm CMOS technology showed that the accuracy of the produced sine is lower than that reported from implementations in bipolar and BiCMOS technologies (dos Reis Filho and Fruett, Proc. ICECS'97, 1997). The measured deviation from ideal sine over the (-π/2 to +π/2) range is less than 0.5%. Total harmonic distortion measured for a fundamental frequency at 20 kHz and the next four harmonics is approximately 1%. This circuit could be used in several applications, including the AC excitation of bridge-type sensors as a replacement for sinusoidal oscillators. View full abstract»

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  • High power four channel IGBT driver IC

    Page(s): P013-1 - P013-6
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    A solution is presented for the monolithic integration of up to four low side drivers inside full bridge power conversion systems. Inexpensive 1 μm high voltage CMOS technology was used in order to keep costs down. It was thus necessary to design special level shifter circuits to facilitate the use of negative turn off voltages. Output currents up to 3.5 A per stage, high insensibility to ESD, soft turn off on short-circuiting, and a complex internal fault management are additional key features. The driver transistors, which are optimized for capacitive loads, control IGBTs up to 1200 V and 150 A per stage. View full abstract»

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  • Active filtering for single phase systems using a modified switching technique

    Page(s): P019-1 - P019-4
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    The use of a fixed switching frequency in the control of active filters produces considerable carrier components in the compensated system current. In this work a modified switching technique is proposed to reduce the amplitude of the carrier component for single phase systems. View full abstract»

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  • A folded-cascode switched OTA based on current deviation

    Page(s): C024 - C1-4
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    An improved version of a fully differential folded-cascode OTA (operational transconductance amplifier), switched at 16 MHz with a single 3 V supply voltage, is presented. The switching process is performed by current deviation at the OTA output stage, instead of turning off its bias current or interrupting the current path from the power supply. Theoretical results show the relationship between the sampling frequency and the folded-cascode OTA design parameters. Simulated results using HSPICE show that the current through the transistors at the OTA output stage is switched properly. View full abstract»

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  • On chip measurement of IC(VBE) characteristics for high accuracy bandgap applications

    Page(s): D025-1 - D025-6
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    The EG and XTI coefficients are sufficient to completely characterise the temperature dependence of IC(VBE) relationship of bipolar transistors (BJT). They are usually obtained from measured VBE(T) values, using least square algorithm at a constant collector current. This method involves an accurate measurement of VBE and of the operating temperature. We propose in this paper, a configurable test structure dedicated to the extraction of the temperature dependence of IC(VBE) characteristic for the BJT designed with bipolar or BiCMOS processes. This allows a direct measurement of the die temperature and consequently an accurate measurement of VBE(T). First, the classical extraction method is explained. Then, the implementation technique of the new method is discussed and finally, an improvement of a bandgap design is presented. View full abstract»

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  • Reuse issues on the verification of embedded MCU cores

    Page(s): C012-1 - C012-6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (538 KB) |  | HTML iconHTML  

    The main issues related to the verification of cores embedded in a microcontroller unit (MCU) are addressed in this paper. Issues such as verification environment design, simulation pattern strategies and reuse, as well as standalone and chip level verification are discussed. An analysis of the verification environment is performed from the perspective of the reuse across the design cycle, focussing on the core standalone and on the chip level verification. A case study analysis is included. View full abstract»

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  • Applying device simulation for lifetime-controlled devices

    Page(s): D029-1 - D029-6
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    Irradiation techniques are widely used for carrier lifetime control in power devices. Improvements of irradiated devices were usually realized by a number of experiments. The use of an extended recombination model allows improved device simulations which explain the temperature dependencies of stationary and dynamical characteristics. Due to that progress device simulation is able to support development and optimization of irradiated devices. View full abstract»

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  • Dynamic logic styles with improved noise-immunity

    Page(s): C031-1 - C031-5
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    Noise issues are becoming an important concern in digital systems due to the aggressive scaling trends in devices and interconnections. Noise effects in deep submicron CMOS VLSI circuits have an importance comparable to area, delay and power consumption. To address this problem a new noise-tolerant dynamic circuit technique suitable for dynamic logic styles is presented. Simulation results show that the proposed technique improves the ANTE (Balamurugan and Shanbhag, IEEE J. Solid-State Circ., vol. 36, no. 2, pp. 273-280, 2001) by 3.4× and 2.8× over conventional dynamic true single-phase-clock (TSPC) and Domino logic, respectively. The improvement in the ANTE-delay quotient is 2.8× and 2.25× over conventional dynamic logic, 2.0× and 1.7× over twin-transistor technique, 1.7× and 1.04× over Bobba's technique for CMOS TSPC and Domino AND gates, respectively. View full abstract»

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  • The influence and modeling of process variation and device mismatch for analog/rf circuit design

    Page(s): D046-1 - D046-8
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    The influence of local process variation and device mismatch to the electrical characteristics of resistors, capacitors, and MOSFETs is reviewed. The discussion is mainly focus on the device mismatch as it becomes more and more important in analog design utilizing modern CMOS technology. The models to describe the mismatch behavior are also discussed. To reduce the design circle/cost and help improving the circuit yields, physical and accurate statistical modeling approach is needed to predict correctly the circuit behavior with the consideration of local process variation and device mismatch. With including the physical correlations between the independent variable and model parameters such models can predict the measured data well at different bias conditions for devices with wide geometries. For the model to be predictive, besides the well known physical effects such as short and narrow width effects, the influence of new physics effects such as poly-gate depletion and channel quantization to process variation and mismatch should be accounted for to describe the device/circuit behaviors correctly. View full abstract»

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  • A low voltage CMOS implementation of a linear cellular neural network for image processing applications

    Page(s): C026-1 - C026-6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (443 KB) |  | HTML iconHTML  

    This paper describe the design of a basic cell for the implementation of a Linear Cellular Neural Network (LCNN). This kind of system could be considered as resistive networks but as its basis are a new way of analog image processing system based on bayesian estimation and regularization theory then a new class of Cellular Neural Networks (CNN), whose activation function is a linear function, emerge in a natural way. This LCNN has characteristic that enable gray-scale image processing. The main focus in this work is the Low Voltage CMOS (LVCMOS) design of the basic building blocks that compose the basic cell of this systems. The design was fabricated on a 0.18 μm LVCMOS technology. View full abstract»

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  • A comparison of Spice-based and carrier transport based simulations of plasma spread in thyristors

    Page(s): D039-1 - D039-4
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    The transient current density distribution in the plane XZ parallel to the electrodes of thyristors and other 4-layer devices is of interest. Since numerical simulations based on the carrier transport equations that include the XZ plane would have to be carried out in 3D, they would become time consuming and expensive. Spice-based XZ simulators as reported in literature are much faster, but the results depend strongly on the necessarily simple equivalent circuits that are used. This paper compares plasma spread simulations in a thyristor, done with an XZ Spice-based simulator previously reported by the authors, with 2D-XY simulations based on the carrier transport equations. It found that for the simulated structure, plasma spread velocity deviates +38% at the beginning of the transient, and -32% near the end of it. On the other hand, for the XZ simulations, it is assumed that the anode current is perpendicular to the XZ plane, and, therefore, the number of discrete elements depend on the extent of validity of that assumption. From the XY simulations it is confirmed that the current flow is almost parallel to the Y direction, making possible high degrees of XZ discretizations. View full abstract»

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  • Wide band gap electronic devices

    Page(s): D051-1 - D051-8
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    The feature sizes of silicon devices approach values where fundamental physics limitations lead to diminishing returns on investment in further scaling, and wide band gap semiconductor materials look increasingly attractive for many applications, where high electron mobility, high current carrying capabilities, a high thermal conductivity, high temperature operation, and a high breakdown field make them superior to silicon and III-V semiconductor technology. GaN-based devices have demonstrated high-temperature operation with little or no degradation up to 300°C. The most spectacular results have been obtained for AlGaN/GaN microwave power High Electron Mobility Transistors (HEMTs) that yielded over to 11 W/mm power at 10 GHz. The maximum density of the two-dimensional electron gas at the GaN/AlGaN heterointerface or in GaN/AlGaN quantum well structures can exceed 2×1013 cm-2, which is an order of magnitude higher than for traditional GaAs/AlGaAs heterostructures. Very large piezoelectric constants of AlN and GaN can be used in piezoelectric and pyroelectric sensors and could be taken advantage for enhancing the sheet carrier concentration and reducing leakage current in conventional electronic devices. Recently proposed Strain Energy Band Engineering and Pulsed Atomic Epitaxy techniques should allow us to independently control strain and lattice mismatch by using AlInGaN/GaN heterostructures and should find important applications in power devices. SiO2/AlGaInN/GaN Metal Oxide Semiconductor Heterostructure Field Effect Transistors (MOSHFETs) and SiN/AlGaInN/GaN Metal Insulator Semiconductor Heterostructure Field Effect Transistors (MISHFETs) have exhibited performance superior to that of conventional AlGaN/GaN devices and hold promise for power applications. GaN epitaxial layers can be grown on SiC, which allows us to combine superior transport properties of GaN with a high thermal conductivity of SiC. All this gives hope that electronic devices based on GaN will reach the same prominence as GaN-based blue and white, and UV light emitters. View full abstract»

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  • Analysis of the gain effect in one-dimension active photonic crystals

    Page(s): D037-1 - D037-5
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    Optical gain-enhancement in active one dimensional photonic crystals is investigated as a function of the characteristic parameters of the system. Using the transfer matrix method, and applying the Bloch theorem, the dispersion relation and the analytical expression relating the gain coefficient to the system parameters (such as the period of the structure, contrast of the refractive indices, geometry of the primitive cell, as well as the number of primitive cells creating the photonic crystal) have been derived. It is shown that the geometry of the primitive cell, as well as the number of primitive cells of which the photonic crystal consists, have a crucial influence on the gain enhancement of the photonic structure. View full abstract»

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  • Design of an LVCMOS high resolution frequency synthesizer

    Page(s): C021-1 - C021-5
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    This work presents the design and implementation of a high frequency high resolution clock synthesizer. A phased-locked-loop (PLL) with internal feedback is the core of the synthesizer. The operating frequency range of the PLL oscillator is 1 GHz to 2 GHz. High resolution is achieved by a wide range programmable feedback divider from 1 to 1024 divide factors in steps of 1. A programmable current mode charge pump is designed to manage the wide range feedback divider. Circuit simulation results demonstrate design feasibility. The design was implemented on a 0.18 μm low voltage CMOS (LVCMOS) technology. View full abstract»

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  • Enhanced coder with error resilience

    Page(s): T029-1 - T029-3
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    A scalable video coder produces a bit stream, decodable at different bit rates. It can substantially improve the quality of video transmitted over error prone channels such as Internet or wireless. The scalable video coding utilizes motion prediction to achieve higher compression efficiency. Since motion compensation is used to reduce temporal redundancy, the quality of the decoded video may decay due to the propagation of errors in the temporal domain. Hence, the double-vector motion compensation (DMC) is used in the scalable video coder, which is implemented in this work. Search strategies based on gradient-descent methods are used. In this study, error concealment techniques are used, which estimate the lost motion vectors by exploiting correlation within the video sequences. View full abstract»

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  • The interaction of hot electrons and hot holes on the degradation of P-channel metal oxide semiconductor field effect transistors

    Page(s): D026-1 - D026-3
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    The hot carrier degradation mechanisms for P Channel metal-oxide-semiconductor (MOS) field effect transistor (PFET) has been investigated. We have established that the dominant hot carrier degradation mechanism for PFET damage changes depending on stress conditions. The coexistence and interaction of hot electrons and hot holes is reported. At the accelerated stress condition where both hot electrons and hot holes exist, the observed hot carrier degradation exhibits a different behavior from that seen in the case when the hot electrons or hot holes are considered separately. A high defect generation rate is reported at the coexistence conditions. We attribute this behavior to the interaction mechanism between hole electrons and hot holes. The electron traps caused by hot electrons recombine with hot holes and facilitate a higher hole trap generation rate. Contrary to conventional thinking we report that the worst case hot carrier degradation degradation condition is not at high Vg but in the coexistence regime. View full abstract»

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  • Sixth-order all-pass filters with OTAs and their characteristics

    Page(s): C035-1 - C035-5
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    In the paper a generalized approach is published with the help of which the sensitivities of frequency filters can by determined. This method of sensitivity calculation is particularly suitable for comparing the sensitivity characteristics of filters from the viewpoint of sensitivity to all the parameters. The approach is used at the juxtaposition of the sensitivity characteristics of two new sixth-order all-pass filters with OTA. View full abstract»

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