By Topic

Microelectronics, 2002. MIEL 2002. 23rd International Conference on

Date 12-15 May 2002

Go

Filter Results

Displaying Results 1 - 25 of 85
  • 2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (358 KB)  

    The following topics are dealt with: power devices and ICs; microsystem technologies; passive devices; optoelectronic and microwave devices; semiconductor physics and characterisation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Author index

    Page(s): 789 - 794
    Save to Project icon | Request Permissions | PDF file iconPDF (174 KB)  
    Freely Available from IEEE
  • Internet-based software for teaching test of digital circuits

    Page(s): 659 - 662
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (225 KB) |  | HTML iconHTML  

    A new teaching concept for teaching testing issues in digital design, which supports the possibility of distance learning as well as a Web-based computer-aided teaching is presented. It offers a set of tools ("interactive modules") to inspect the teaching topics and to carry out laboratory research. The interactive modules are focused on easy action and reaction, learning by doing, a game-like use, and fostering students in critical thinking, problem solving skills and creativity View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A novel data writing method in a 1T2C-type ferroelectric memory

    Page(s): 517 - 520
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB) |  | HTML iconHTML  

    A novel data writing method is proposed in a 1T2C-type ferroelectric memory, in which two ferroelectric capacitors with the same area are connected to the gate electrode of a MOSFET. The writing method has such an advantage that the ferroelectric capacitors are well polarized, even if the gate capacitance is relatively large. A cell structure suitable for this writing method is also proposed, which has another advantage that the cell array can easily be fabricated. SPICE simulation shows that stable operation of this cell can be expected when the device parameters are optimized View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Mixed-level defect simulation in data-paths of digital systems

    Page(s): 617 - 620
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (222 KB) |  | HTML iconHTML  

    A new method for mixed level fault simulation of Data-Paths in Digital Systems represented with Decision Diagrams (DD) is proposed. We suppose that a register transfer level (RTL) information along with gate-level descriptions for RTL blocks are available. Decision diagrams (DDs) are exploited as a uniform model for describing circuits on both levels. The physical defects in the system are mapped to the logic level and are simulated on the mixed gateand RT levels. The approach proposed allows to increase the accuracy of test quality estimation, and to reduce simulation cost in comparison to traditional gate-level fault simulation methods View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Channel-carrier mobility parameters for 4H SiC MOSFETs

    Page(s): 425 - 430 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (324 KB) |  | HTML iconHTML  

    In this paper, mobility parameters for n-channel 4H SiC MOSFETs are extracted and implemented into 2D device simulation program and SPICE circuit simulator. The experimental data were obtained from lateral n-channel 4H SiC MOSFET's with nitrided oxide-semiconductor interface, exhibiting normal mobility behavior. The effects of interface-trap density on the model parameters are discussed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Power saving modes in modern microcontroller design and chip diagnostics

    Page(s): 593 - 596
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (226 KB) |  | HTML iconHTML  

    This paper is targeting some of the most important problems in modern microcontroller-on-chip design: low power consumption and efficient chip diagnostics. A case study of a microcontroller device is presented. Applied system-level techniques for dynamic power saving are described. Chip diagnostic methods are developed that are based on measuring of the supply current in different power saving modes View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On efficient logic-level simulation of digital circuits represented by the SSBDD model

    Page(s): 621 - 624 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (227 KB) |  | HTML iconHTML  

    Logic-level simulation is still one of the most often used operations on digital designs during both design and test stages. This makes it a critical issue affecting the overall cost of a project. In this paper we investigate and show the origins of common advantages of four recently proposed efficient simulation methods of different classes: logic simulation, multi-valued simulation, timing simulation, and fault simulation. Described advantages became possible due to use of a highly efficient model called Structurally Synthesized Binary Decision Diagrams (SSBDD). This very compact model preserves the structural information about the modeled circuit and utilizes circuit partitioning into a set of macros represented each by its own SSBDD. All this makes the SSBDD model a good choice as a logic-level digital design representation. The analysis is made on the basis of experimental data acquired using ISCAS'85 benchmark circuits. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Unified MOSFET scaling theory using variational method

    Page(s): 491 - 494
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    Using the variational method, the two dimensional Poisson Equation is solved in the MOSFET device region including the gate oxide region, depletion region and buried oxide region (for SOI device). An analytical expression for the potential distribution together with a new natural gate length scale for MOSFET is derived. The 2-D effects in front gate dielectric, back gate dielectric and silicon film can all be taken into account in this derivation. The validity of electrical equivalent oxide thickness approximation is also investigated using this model. Comparison of the short channel effect for uniform channel doping bulk MOSFET, intrinsic channel doping bulk MOSFET, SOI MOSFET and double gated MOSFET is conducted using our model. The results are verified by 2D numerical simulation using the 2D device simulator MEDICI View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Compact modeling for SiGe HBTs

    Page(s): 459 - 462 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (453 KB)  

    Compact modeling techniques that handle peculiar features of SiGe HBTs are presented and analyzed. An appropriate generalization of the Early factor is proposed. Numerical device simulation for two typical SiGe transistor structures with different dopant profiles and Ge mole fractions is used as a basis for the model evaluation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A calibrated model for silicon self-interstitial cluster formation and dissolution

    Page(s): 431 - 434 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (269 KB) |  | HTML iconHTML  

    The formation and dissolution of Silicon self-interstitial clusters is linked to the phenomenon of TED (transient enhanced diffusion) which in turn has gained importance in the manufacturing of semiconductor devices. Based on theoretical considerations and measurements of the number of self-interstitial clusters during a thermal step we were interested in finding a suitable model for the formation and dissolution of self-interstitial clusters and extracting corresponding model parameters for two different technologies (i.e., material parameter sets). In order to automate the inverse modeling part a general optimization framework was used. Additional to solving this problem the same setup can solve a wide range of inverse modeling problems occurring in the domain of process simulation. Finally the results are discussed and compared with a previous model. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Trends in low-voltage embedded-RAM technology

    Page(s): 497 - 501
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (341 KB) |  | HTML iconHTML  

    First, trends in the gate-oxide thickness of MOSFET for DRAM and MPU are discussed to clarify the strong need for low-voltage operation of embedded RAMs. Then, modern peripheral logic circuits for reducing leakage currents, and DRAM/SRAM cells to cope with the ever-decreasing signal charges are described. Finally, needs for developments of subthreshold-current reduction circuits for use in active mode, memory-rich SoC architectures, and gain cells and non-volatile cells are emphasized View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Evaluation of epi layer resistivity effects in mixed-signal submicron CMOS integrated circuits

    Page(s): 569 - 572
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (581 KB) |  | HTML iconHTML  

    This paper illustrates a simple model for calculation and experimental evaluation of epi layer resistance. The model can be used during early stages of mixed-signal integrated circuit design, to estimate the effects of switching noise injection from digital cells to analog circuitry. Moreover, the proposed model leads to a simplified equivalent circuit that can be used for fast SPICE-level simulations of crosstalk effects View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 1D physically based non-quasi-static analog behavioral BJT model for SPICE

    Page(s): 463 - 468 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (495 KB)  

    A compact 1D non-quasi-static BJT model (NQS BJT) based on the analog behavioral modeling capabilities of the SPICE simulator is described. The NQS BJT model parameters are derived directly from the physical device structure. A momentum relaxation time parameter is also included as equivalent inductivity, yielding more accurate prediction of unity gain frequency and phase characteristics. The efficiency of the novel NQS model is demonstrated by comparison with the standard Gummel-Poon model and experimental results. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Generalization of the integral function method to evaluate distortion in SOI FD MOSFET

    Page(s): 443 - 446 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB) |  | HTML iconHTML  

    The harmonic distortion introduced by MOS transistors is a property of major importance regarding their analog applications. In recent papers we presented a new integral function method (IFM) to calculate total harmonic distortion (THD) and the third harmonic component (HD3) of MOSFET based on the direct analysis of the non-linearity of the DC IDS-VDS characteristic of the device for a fixed gate voltage. To evaluate this non-linearity, we defined an integral function, which will be called D hereafter, to calculate an integral equation of the IDS-VDS characteristic, and in order to eliminate the even harmonics, a second function, which we call D3 was also defined. In this paper we generalize the IFM to analyze the case where several MOSFET pairs (balanced 2-MOSFET and double balanced 4-MOSFET structures) are used in order to eliminate the even harmonics. Real transistors always show some mismatch in their parameters that become apparent even in these balanced circuits. For the generalized IFM a new function Da is defined and used to analyze the effect of variation of transistor parameters. The efficiency of the new method is demonstrated analyzing the harmonic distortion in a balanced circuit, where typical variations of the threshold voltage if the transistors is taken into account. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Spontaneous recovery of positive gate bias stressed power VDMOSFETs

    Page(s): 717 - 721
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (255 KB) |  | HTML iconHTML  

    Spontaneous recovery of threshold voltage and channel carrier mobility in positive gate bias stressed power VDMOSFETs and the underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed. Electron tunneling from neutral oxide traps associated with trivalent silicon ≡Sio. defects into the oxide conduction band is proposed as the main mechanism responsible for stress-induced buildup of positive oxide-trapped charge. Subsequent hole tunneling from the charged oxide traps ≡Sio+ to interface-trap precursors ≡Sis-H is proposed as the dominant mechanism responsible for the interface trap buildup. A chain of mechanisms related to a presence of hydrogen species is proposed in order to explain changes of oxide-trapped charge and interface trap densities during the spontaneous recovery. Interface trap ≡Sis . passivation due to their reaction with hydrogen atoms is proposed as a main mechanism responsible for a decrease of interface trap density. Hydrogen molecule cracking at charged oxide traps ≡Sio+, which leads to their neutralization, is proposed as the dominant mechanism responsible for a decrease of oxide-trapped charge density View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Influence of the defects on the I-V characteristics for LDD-nMOSFETs

    Page(s): 471 - 474 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (245 KB) |  | HTML iconHTML  

    Hot-carrier injection is observed increasingly to degrade the I-V characteristics with the scaling of MOS transistors. For the lightly doped drain (LDD) MOS transistor the injection of hot carriers, caused by the high electric field in the MOS structure, is localized in the LDD region. The modeling of the drain current in relation to defects due to the hot-carrier injection allows us to investigate the I-V characteristics and the transconductance of devices. Consequently, we can calculate the amount of device degradation caused by these defects in order to find technological solutions to optimize reliability. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A modified DSOI (Drain/Source On Insulator) device structure with better electrical performance

    Page(s): 487 - 490
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (290 KB) |  | HTML iconHTML  

    A new device structure called DSOI (Drain/Source On Insulator) is proposed to alleviate the thermal transfer problem and floating body effects in SOI (Silicon on Insulator) device. The purpose of present work is to modify DSOI structure to get the best device electrical capability. We focus on the location of buried oxidation. And simulation results approve that this modified structure having better electrical performance than prototype View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Integration issues for polymeric dielectrics in large area electronics [TFTs]

    Page(s): 543 - 546
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (222 KB) |  | HTML iconHTML  

    The issues concerning the integration of polymeric low-permittivity (low-k) dielectrics in amorphous Si (a-Si) thin-film transistor (TFT) arrays have been investigated. A photosensitive spin-on polymer, photo-benzocyclobutene (PBCB), has been studied for integration as interlevel dielectric between the transistor and pixel levels in TFT arrays. The dielectric films were characterized by permittivity, stress, and planarization measurements. The dielectric constant was found to be in the range of 2.5-3.5. The degree of planarization was > 90%, and the film stress was about 60 MPa. Process parameters have been optimized for integration in TFT arrays. Measurements on test structures showed low leakage current and good electrical contact at via interconnections View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Simulation of nanometer-scale MOSFET's with ultra-thin gate oxide including full 2-dimensional quantum mechanical effects and gate tunneling current

    Page(s): 435 - 438 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (333 KB) |  | HTML iconHTML  

    A new simulator is developed including Quantum Mechanical Effects (QMEs) in the whole channel and gate tunneling current along the gate oxide. Schrodinger equation is solved using Modified Airy Function (MAF) method in the whole device including gate electrode, oxide and substrate and thus QMEs and tunneling effects can be taken into consideration at the same time. The simulator has high efficiency and accuracy. Advanced devices are simulated emphasizing QMEs and tunneling current through gate oxide. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Symbolic-numeric co-simulation of large analogue circuits

    Page(s): 639 - 642 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (231 KB) |  | HTML iconHTML  

    This paper presents a new method for hierarchical analysis of large circuits that combine numeric and symbolic simulation. Symbolic analysis is applied only on subcircuits at the lowest hierarchical level. This approach proves beneficial for symbolic and numeric simulation. The time reduction is given on a benchmark example. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low power synthesis based on information theoretic measures

    Page(s): 699 - 702
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB) |  | HTML iconHTML  

    The synthesis of circuits with reduced power consumption has grown more and more important over the last years. In this paper, we address the problem of reduction of power dissipation using dynamic power management techniques. The problem of low power synthesis corresponds to an optimal decomposition of a finite state machine reduced to choice of partitions on the set of states of prototype machine. For evaluation of the networks, the informational modeling based on entropy measure is considered. It enables one to enhance the decomposition partition search for low power synthesis View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Top surface imaging lithography processes for I-line resists using liquid-phase silylation

    Page(s): 503 - 508
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (286 KB) |  | HTML iconHTML  

    In this paper, liquid-phase silylation process for Top Surface Imaging Lithography systems incorporating e-beam exposure has been experimentally investigated using FT-IR spectroscopy, UV spectroscopy, SIM spectrometry and SEM cross-sectionals. The impact of different silylating agents on Shipley SPR505A resist system is presented for both the UV exposed and e-beam crosslinked regions of the resist. Results show that an e-beam dose of 50μC/cm2 at 30keV is sufficient to crosslink the resist and prevent silylation. The silylation contrast using HMCTS was found to be the highest (11:1) in comparison with other two agents. It was found that the silicon incorporation in SPR505A resist follows Case II diffusion mechanisms View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Electromagnetic interference of switching mode power regulator with chaotic frequency modulation

    Page(s): 577 - 580
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (390 KB) |  | HTML iconHTML  

    In this work, we propose an improved switching scheme (called chaotic frequency modulation (CFM)) for switched-mode power supplies to suppress the electromagnetic interference (EMI) noise source. The basic principle of CFM is to use a chaotic signal to modulate the switching signal such that the harmonics of noise power is distributed evenly over the whole spectrum instead of concentrated at the switching frequency. When compared with the conventional pulse width modulation (PWM) scheme, significant improvements in both conducted and radiated EMI noise levels were found with CFM method. For conducted EMI, the peak noise level was reduced by 25 dB. For radiated EMI, we found that the noise was found mainly in the frequency range of 30 MHz to 230 MHz and the CFM scheme would help to reduce the peak noise level in this frequency range by 22 dB View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Formal specification and preliminary design of an asynchronous traffic light controller

    Page(s): 679 - 682
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (194 KB) |  | HTML iconHTML  

    An exercise in formal specification and design of an asynchronous controller that leads to the CMOS implementation is presented. In this paper we focus on the formal specification of the controller by using communication sequential process, a tool based on Hoare's CSP. We also present the procedure, based on Martin's synthesis method, used to formally derive the preliminary design of the asynchronous traffic light controller. The formal specification and circuit implementation are formally verified with a verification tool package STTools, capable of model checking and simulating programs View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.