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Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

Date 8-8 March 2002

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Displaying Results 1 - 25 of 230
  • Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (472 KB)  

    The following topics are dealt with: semiconductor IP; formal verification; cooling; power management; defect oriented test; SAT and BDD techniques; low power design; mixed signal test; collaborative design; logic synthesis; symbolic techniques; EDA tools; analogue circuits; asynchronous circuits; BIST; DFT; co-design; SoC; embedded systems; reconfigurable architectures; analogue modelling; object oriented design; interconnect modelling; fault tolerance; ATPG; high-level synthesis; and IC modelling. View full abstract»

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  • On nanoscale integration and gigascale complexity in the post .com world

    Page(s): 12
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    Summary form only given, as follows. While process technologists are obsessed to follow Moore's curve down to nanoscale dimensions, design technologists are confronted with gigascale complexity. On the other hand, post-PC and post dotcom products require zero cost, zero energy yet software programmable novel system architectures to be sold in huge volumes and to be designed in exponentially decreasing time. How do we cope with these novel silicon architectures? What challenges in research does this create? How to create the necessary tools and skills and how to organize research and education in a world driven by shareholders value? Can you spare half an hour to reflect on these challenges to the design community? View full abstract»

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  • Sizing power/ground meshes for clocking and computing circuit components

    Page(s): 176 - 183
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (351 KB) |  | HTML iconHTML  

    This paper presents a new formulation and an efficient solution of the power and ground mesh sizing problem. We use the key observations that (1) the drops in power and ground node potentials are due not only to currents drawn by the computing blocks, but also to those drawn by the clock buffers, and (2) changes of circuit component delays are linearly proportional to the power/ground IR-drops. This leads to a linear quantification of the timing relations between the clocking and computing components in terms of the power/ground IR-drops. Our method removes all IR-drop related timing violations that occur in about 2% of paths when grids are sized using the existing methods that satisfy the maximum IR-drop constraints. In addition, we achieve supply mesh area improvements of the order of 30% while simultaneously reducing the power dissipated in the circuits by about 6.6% compared to traditional grid sizing methods. View full abstract»

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  • Who owns the platform?

    Page(s): 238
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB)  

    Summary form only given. As VLSI technology advances, it forces changes in the business organization of the industry. Traditional vertically integrated semiconductor manufacturers are concentrating less on manufacturing as foundries such as TSMC, UMC, and Chartered grow. These foundries supply capacity not only to fables houses but also to even large semiconductor manufacturers. As a result, these semiconductor houses are spending more time creating novel platforms for important applications. This puts them in competition with the systems houses that traditionally were their customers. View full abstract»

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  • Power crisis in SoC design: strategies for constructing low-power, high-performance SoC designs

    Page(s): 538
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    Freely Available from IEEE
  • Panel: Reconfigurable SoC- What will it look like

    Page(s): 660 - 662
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    Freely Available from IEEE
  • Closed-form crosstalk noise metrics for physical design applications

    Page(s): 812 - 819
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB) |  | HTML iconHTML  

    In this paper we present efficient closed-form formulas to estimate capacitive coupling-induced crosstalk noise for distributed RC coupling trees. The efficiency of our approach stems from the fact that only the five basic operations are used in the expressions: addition (x+y), subtraction (x-y), multiplication (x/spl times/y), division (x/y) and square root (/spl radic/x). The formulas do not require exponent computation or numerical iterations. We have developed closed-form expressions for the peak crosstalk noise amplitude, the peak noise occurring time and the width of the noise waveform. Our approximations are conservative and yet achieve acceptable accuracy. The formulas are simple enough to be used in the inner loops of performance optimization algorithms or as cost functions to guide routers. They capture the influence of coupling direction (near-end and far-end coupling) and coupling location (near-driver and near-receiver). View full abstract»

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  • European CAD from the 60's to the new millenium

    Page(s): 992
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (213 KB)  

    Summary form only given, as follows. Computer-aided design (CAD) has always been hardly understood by the CEO's of companies because it obeys rules (if any) very different from the process. A rich variety of CAD and TCAD solutions have been developed in Europe in the early days of the CAD industry. These solutions have come to introduce real innovations in the field, but because they were mostly internal to the companies they have never reached the proper engineering level that would have enabled their introduction in the market. A review of the CAD history activity in Europe will be presented in this Plenary Session, together with some prospects on how it could evolve in the coming years and change from its lackluster industrial visibility. View full abstract»

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  • Author index

    Page(s): 1141 - 1147
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    Freely Available from IEEE
  • An efficient test and diagnosis scheme for the feedback type of analog circuits with minimal added circuits

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (173 KB)  

    This paper presents a test and diagnosis scheme for feedback type of linear analog circuits with minimal added circuits. For testing, the scheme transforms the circuit-under-test (CUT) into an oscillation circuit by (1) increasing the loop gain of the circuit, and/or (2) reconfiguring the circuit through selectively powering-off operational amplifiers (OP) of the circuit. This eliminates the need of added global paths as in the conventional oscillation test scheme. For diagnosis, the scheme transforms the circuit into a Schmitt trigger type of circuit with a positive-feedback. The output of the circuit under an applied triangular input gives signatures which are used to identify faults. Benchmark circuits have been applied with this scheme and results show that it is very effective for testing and diagnosing the feedback type of linear analog circuit. View full abstract»

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  • FPGA placement by thermodynamic combinatorial optimization

    Page(s): 54 - 60
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2525 KB)  

    In this paper, the placement problem on FPGAs is faced using thermodynamic combinatorial optimization (TCO). TCO is a new combinatorial optimization method based on both thermodynamics and information Theory. In TCO two kinds of processes are considered: microstate and macrostate transformations. Applying the Shannon's definition of entropy to microstate reversible transformations, a probability of acceptance based on Fermi-Dirac statistics is derived On the other hang applying thermodynamic laws to reversible macrostate transformations, an efficient annealing schedule is provided TCO has been compared with simulated annealing (SA) on a set of benchmark circuits for the FPGA placement problem. TCO has achieved large time reductions with respect to SA, while providing interesting adaptive properties View full abstract»

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  • Concurrent and selective logic extraction with timing consideration

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB) |  | HTML iconHTML  

    We study the problem of concurrent and selective logic extraction in a Boolean circuit. We first model the problem using graph theory, prove it to be NP-hard, and subsequently formulate it as a Maximum-Weight Independent Set problem in a graph. We then use efficient heuristics for solving the MWIS problem. Concurrent logic extraction not only allows us to achieve larger literal saving and smaller area due to a more global view of the extraction space, but also provides us with a framework for reducing the circuit delay View full abstract»

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  • On the use of an oscillation-based test methodology for CMOS micro-electro-mechanical systems

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (318 KB) |  | HTML iconHTML  

    This paper introduces the use of the oscillation test technique for MEMS testing. This well-known test technique is here adapted to MEMS. Its efficiency is evaluated based on a case study: A CMOS electromechanical magnetometer. View full abstract»

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  • Techniques to evolve a C++ based system design language

    Page(s): 302 - 309
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (268 KB) |  | HTML iconHTML  

    Complex systems-on-chip present one of the most challenging design problems. To meet this challenge, new design languages capable of modelling such heterogeneous, dynamic systems are needed. For implementation of such a language, the use of an object oriented C++ class library has proven to be a promising approach, since new classes dealing with design- and platform-specific problems can be added in a conceptual and seamlessly reusable way. This paper shows the development of such an extension aimed to provide a platform-independent high-level structured storage object through hiding of the low-level implementation details. It results in a completely virtualised, user-extendible component, suitable for use in heterogeneous systems View full abstract»

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  • Practical instruction set design and compiler retargetability using static resource models

    Page(s): 1021 - 1026
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (259 KB) |  | HTML iconHTML  

    The design of application (-domain) specific instruction-set processors (ASIPs), optimized for code size, has traditionally been accompanied by the necessity to program assembly, at least for the performance critical parts of the application. The highly encoded instruction sets simply lack the orthogonal structure present in e.g. VLIW processors, that allows efficient compilation. This lack of efficient compilation tools has also severely hampered the design space exploration of code-size efficient instruction sets, and correspondingly, their tuning to the application domain. In Zhao et al (Proc. 14th Int. Symp. on System Synthesis, 2001), a practical method is demonstrated to model a broad class of highly encoded instruction sets in terms of virtual resources easily interpreted by classic resource constrained schedulers (such as the popular list-scheduling algorithm), thereby allowing efficient compilation with well understood compilation tools. In this paper we will demonstrate the suitability of this model to also enable instruction set design (-space exploration) with a simple, well-understood and proven method long used in the high-level synthesis (HLS) of ASICs. A small case study proves the practical applicability of the method View full abstract»

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  • An interconnect-aware methodology for analog and mixed signal design, based on high bandwidth (over 40 GHz) on-chip transmission line approach

    Page(s): 804 - 811
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (364 KB) |  | HTML iconHTML  

    This paper presents an on-chip, interconnect-aware methodology for high-speed analog and mixed signal (AMS) design which enables early incorporation of on-chip transmission line (T-line) components into AMS design flow. The proposed solution is based on a set of parameterized T-line structures, which include single and two coupled microstrip lines with optional side shielding, accompanied by compact true transient models. The models account for frequency dependent skin and proximity effects, while maintaining passivity requirements due to their pure RLC nature. The signal bandwidth supported by the models covers a range from DC to 100 GHz. The models are currently verified in terms of S-parameter data against hardware (up to 40 GHz) and against EM solver (up to 100 GHz). This methodology has already been used for several designs implemented in SiGe (silicon-germanium) BiCMOS technology. View full abstract»

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  • Top-down system level design methodology using SpecC, VCC and SystemC

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (204 KB) |  | HTML iconHTML  

    In this paper we suggest a top-down methodology from C to silicon. In our methodology, we focus on methods to make the design flow smooth, efficient, and easy. The proposed methodology is a pure top-down methodology. We developed our design methodology by using SpecC, VCC, and SystemC. We choose SpecC, VCC and SystemC because they are all C-related and each have strong support in at least one field of design. Our proposal for a methodology is based on our experiences of attempting to model the JPEG encoder with SpecC, SystemC and VCC, and one internal project, attempting to implement architecture exploration for MPEG encoding and decoding using VCC View full abstract»

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  • A new ATPG algorithm to limit test set size and achieve multiple detections of all faults

    Page(s): 94 - 99
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (329 KB) |  | HTML iconHTML  

    Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduces the overall defective part level. However, multiple observations of each fault site lead to increased test set size and require more tester memory. In this paper we propose a new ATPG algorithm to find a near-minimal test pattern set that detects faults multiple times and achieves excellent defective part level. This greedy approach uses 3-value fault simulation to estimate the potential value of each vector candidate at each stage of ATPG. The result shows generation of a close to minimal vector set is possible only using dynamic compaction techniques in most cases. Finally, a systematic method to trade-off between defective part level and test size is also presented View full abstract»

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  • AccuPower: an accurate power estimation tool for superscalar microprocessors

    Page(s): 124 - 129
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (231 KB) |  | HTML iconHTML  

    This paper describes the AccuPower toolset-a set of simulation tools accurately estimating the power dissipation within a superscalar microprocessor. AccuPower uses a true hardware level and cycle level microarchitectural simulator and energy dissipation coefficients gleaned from SPICE measurements of actual CMOS layouts of critical datapath components. Transition counts can be obtained at the level of bits within data and instruction streams, at the level of registers, or at the level of larger building blocks (such as caches, issue queue, reorder buffer function units). This allows for an accurate estimation of switching activity at any desired level of resolution. The toolsuite implements several variants of superscalar datapath designs in use today and permits the exploration of design choices at the microarchitecture level as well as the circuit level, including the use of voltage and frequency scaling. In particular the AccuPower toolsuite includes detailed implementations of currently used and proposed techniques for energy/power conservations including techniques for data encoding and compression, alternative circuit approaches, dynamic resource allocation and datapath reconfiguration. The microarchitectural simulation components of AccuPower can be used for accurate evaluation of datapath designs in a manner well beyond the scope of the widely-used Simplescalar tools View full abstract»

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  • Optimal transistor tapering for high-speed CMOS circuits

    Page(s): 708 - 713
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (261 KB) |  | HTML iconHTML  

    Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in high-performance circuit design with a view to minimizing the delay of a FET network. Currently, in a long series-connected FET chain, the dimensions of the transistors are decreased from bottom transistor to the top transistor in a manner where the width of transistors is tapered linearly or exponentially. However, it has not been mathematically proved whether either of these tapering schemes yields optimal results in terms of minimization of switching delays of the network. In this paper, we rigorously analyze MOS circuits consisting of long FET chains under the widely used Elmore delay model and derive the optimality of transistor tapering by employing variational calculus. Specifically, we demonstrate that neither linear nor exponential tapering alone minimizes the discharge time of the FET chain. Instead, a composition of exponential and constant tapering actually optimizes the delay of the network. We have also corroborated our analytical results by performing extensive simulation of FET networks and showing that both analytical and simulation results are always consistent View full abstract»

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  • An enhanced Q-sequence augmented with empty-room-insertion and parenthesis trees

    Page(s): 61 - 68
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (319 KB) |  | HTML iconHTML  

    After the discussion on the difference between floorplanning and packing in VLSI placement design, this paper adapts the floorplanner that is based on the Q-sequence to a packing algorithm. For the purpose, some empty room insertion is required to guarantee not to miss the optimum packing. To increase the performance in packing, a new move that perturbs the floorplan is introduced in terms of the parenthesis-tree pair. A simulated annealing based packing search algorithm was implemented. Experimental results showed the effect of empty room insertion View full abstract»

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  • Improved technology mapping for PAL-based devices using a new approach to multi-output boolean functions

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (217 KB) |  | HTML iconHTML  

    An effective technology mapping for PAL-based devices is presented in this paper. The aim of this method is to cover a multiple-output function by a minimal number of PAL-based logic blocks. The product terms included in a logic block can be shared by several functions. Experimental results are compared to the classical technology mapping method View full abstract»

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  • Directed-binary search in logic BIST diagnostics

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (292 KB) |  | HTML iconHTML  

    Logic BIST is about to become a more main stream test method for IC testing. In some flows when a failure is encountered the IC is diagnosed to determine the cause of the failure. Diagnosing fails in Logic BIST is significantly different from that in a stored pattern test methodology. The first step is to determine the failing pattern or interval among the many patterns that were applied. Today this involves a binary search of the tests that were applied with Logic BIST. In this paper we improve on this binary search strategy to reduce the time taken to isolate the failing patterns by orders of magnitude. View full abstract»

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  • Test structure for IC(VBE) parameter determination of low voltage applications

    Page(s): 316 - 321
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (377 KB) |  | HTML iconHTML  

    The temperature dependence of the IC(VBE) relationship can be characterised by two parameters: EG and X TI. The classical method to extract these parameters consists in a "best fitting" from measured VBE(T) values, using least square algorithm at constant collector current. This method involves an accurate measurement of YBE voltage and an accurate value of the operating temperature. We propose in this paper, a configurable test structure dedicated to the extraction of temperature dependence of Ic(VBE) characteristic for BJT designed with bipolar or BiCMOS processes. This allows a direct measurement of die temperature and consequently an accurate measurement of VBE(T). First, the classical extraction method is explained. Then, the implementation techniques of the new method are discussed, the improvement of the design is presented View full abstract»

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