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Microelectronics, 2001. ICM 2001 Proceedings. The 13th International Conference on

Date 29-31 Oct. 2001

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Displaying Results 1 - 25 of 67
  • A CMOS single-CCII+ based VCO

    Publication Year: 2001 , Page(s): 165 - 168
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (355 KB) |  | HTML iconHTML  

    In this paper we have designed and implemented a voltage controlled oscillator (VCO) based on the single positive CMOS second generation enhanced current conveyor (CCII+) using a standard low-cost CMOS technology. The proposed circuit is fully characterized by both simulation and measurements. View full abstract»

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  • Design and verification of an ATM Knockout switch concentrator

    Publication Year: 2001 , Page(s): 261 - 264
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (463 KB) |  | HTML iconHTML  

    In this paper we describe the design and verification of the concentrator of a Knockout ATM (Asynchronous Transfer Mode) switch fabric using the VIS tool. The Knockout is a popular ATM switch fabric which has application in both datagram and virtual circuit packet networks. The concentrator is the most difficult component in the Knockout ATM switch fabric. We developed an RTL structural design as well as a higher-level behavioral model of the Knockout switch concentrator in Verilog HDL. We then used equivalence checking within VIS to verify the concentrator structure against its behavioral model. While sequential equivalence checking failed, we succeeded the combinational equivalence checking of a latch-reduced model of the concentrator. View full abstract»

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  • Regeneration techniques for RLC VLSI interconnects

    Publication Year: 2001 , Page(s): 209 - 212
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (459 KB) |  | HTML iconHTML  

    On-chip inductance has become of significance in the design of high-speed interconnects. In this paper, three techniques are applied to regenerate an RLC interconnect in series, parallel and without regeneration. Simulations using a 0.25 μm TSMC technology show that the parallel regeneration starts achieving a better speed than the non-regenerated line at wire lengths smaller than that achieved when the wire is serially regenerated. It also features 47% time delay saving and 96% area-delay product saving over the serial regeneration. View full abstract»

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  • Novel varactors in BiCMOS technology with improved characteristics

    Publication Year: 2001 , Page(s): 59 - 62
    Cited by:  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (507 KB) |  | HTML iconHTML  

    The first true BiCMOS varactor combining typical elements of CMOS and bipolar Technologies is presented. Several test structures and different versions have been manufactured in a 0.25 μm BiCMOS technology and measured. The first type of the proposed novel varactor structure features a capacitance tuning range (ratio of maximum to minimum achievable values) Cmax/Cmin of 3.8:1 with a minimum quality factor Q of 32 and a maximum Q of 273. Choosing the second type of the herein presented novel device, allows quality factors from 6 to above 500, while increasing the capacitance tuning range to an outstanding value of 10.11:1. View full abstract»

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  • E-commerce new trends: Virtual Design Support Center (VDSC)

    Publication Year: 2001 , Page(s): 265 - 268
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (437 KB) |  | HTML iconHTML  

    Learning on-line is one of the fastest moving trends in higher education as engineers and executives in technology industries are discovering. Today, thanks to the widespread access to the Internet, on-line education is enabling professional for continues learning and keeping pace with technological and managerial changes despite their heavy schedule. In this paper we will discuss the importance of E-learning in electronics technology as well as the need for the Virtual Design Support Center (VDSC). View full abstract»

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  • New method for determination of drain saturation voltage in submicrometer MOSFETs between liquid helium to room temperature

    Publication Year: 2001 , Page(s): 63 - 64
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (268 KB) |  | HTML iconHTML  

    A new method for drain saturation voltage extraction in submicron MOSFETs is presented. It is based on measurements of the partial derivative of the impact ionization rate. The method has been tested using different channel length MOSFET devices and compared with other methods. View full abstract»

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  • New current-mode all-pass configuration using CCCIIs

    Publication Year: 2001 , Page(s): 157 - 160
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (314 KB)  

    In this paper a new configuration for the realization of first-order current-mode all-pass filters with high output impedance is presented. It can realize first-order allpass filtering function using two current controlled conveyors (CCCIIs) connected to four RC one-port elements. Eight different realizations for the proposed configuration are given in tabular form, which exhibit identical transfer functions but differ in the number of passive components, component matching constraints, possibility of electronic gain adjustment and other properties. PSPICE simulation results are given to confirm the theoretical analysis. View full abstract»

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  • The study of a drift-diffusion model

    Publication Year: 2001 , Page(s): 54 - 58
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (395 KB) |  | HTML iconHTML  

    This work proposes a theoretical and a numerical study of a decoupled algorithm in order to approximate a free boundary separating the depletion region and the charge neutrality region in a field effect transistor of MESFET type. In order to do that, a simplified drift-diffusion model is used. In this work we prove the convergence of the previous algorithm and we present some numerical results. View full abstract»

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  • An accurate method for extracting the critical field in short channel NMOS devices

    Publication Year: 2001 , Page(s): 65 - 66
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (279 KB) |  | HTML iconHTML  

    In this paper, an accurate method for extracting the critical field Ec in short channel MOSFET's is presented. The principle of this method is based on the comparison between two models which give drain saturation voltage evolution against gate voltage Vdsat(Vg) continuously. The results obtained by this technique have shown better agreement with measurement data and have allow at the same time to determine the validity domain of Sodini's law. View full abstract»

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  • Interface state degradation of metal/ultra-thin oxide/semiconductor structures under electron injections at high field

    Publication Year: 2001 , Page(s): 67 - 70
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (483 KB) |  | HTML iconHTML  

    In this paper we analyze the interface states of metal/ultra thin oxide/semiconductor structures and their degradation under electron injection from the metal or the semiconductor, by the Fowler-Nordheim effect, at high electric field (>10 MV/cm). The metal used is chromium and the oxide layer thickness is in the range of 60 Å-130 Å. Before injection the energy distribution of the interface states in the semiconductor gap presents a peak of energy of 0.25 eV above the semiconductor valence band edge. The peak density (Nssmax) decreases with the oxide thickness. After injection the degradation of the Nssmax density depends on the oxide thickness, and increases with injected charge independently of the injected field and the polarization mode (V<0, V>0) of the structure for the high injected charge (Qinj>2.10-1 c/cm2). The injection influence on the interface state density (Nssmid) at mid gap is not important. The Nssmid density is lower than 1010 eV-1 cm-2 for all the injection charges (V<0, V>0). Also, we showed that the sensitivity to the degradation by electron injection decreases with the oxide thickness. In comparing with the literature results, we deduced a lower interface state density for our structures, and a satisfactory sensitivity to the degradation to high injecting fields. View full abstract»

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  • A polynomial division pipelined architecture for CRC error detecting codes

    Publication Year: 2001 , Page(s): 133 - 136
    Cited by:  Patents (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (394 KB) |  | HTML iconHTML  

    Error detection in telecommunication applications is frequently ensured with CRC (Cyclic Redundancy Checking). However, the evolution towards increasing data rates increases the need for more and more sophisticated implementations. In this paper, we present an effective architecture for the CRC function based on a pipelined implementation of the polynomial division. It improves very effectively the speed performance, allowing data rates from 1 Gbit/s to 4 Gbit/s on FPGA implementations, according to the parallelisation level (8 to 32 bit). View full abstract»

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  • A hardware accelerator for DSP system design: University of Tehran DSP Hardware Emulator (UTDHE)

    Publication Year: 2001 , Page(s): 141 - 144
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (408 KB) |  | HTML iconHTML  

    DSP systems play an important role in modern industry and new DSP systems should be designed rapidly to overcome the new necessities that arise. However, the process of designing a DSP system is very time consuming and most of this time is wasted on simulating and debugging of such complex systems. We have designed and implemented a system that makes it possible to emulate and debug large DSP designs (up to 250,000 gates) as fast as possible. With this system, the user can test his or her DSP scheme with fast hardware emulation instead of slow software simulation and as a result reduce time to market significantly. The designed DSP HWE system can emulate complex DSPs that operate at different clock rates and need up to four modules of external memories. It is important to note that low-level simulation of such systems needs a long simulation time, making it impossible to completely simulate and test such designs. As a result of this work, such prohibitive factor has been eliminated. View full abstract»

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  • New hardware/software design methodologies

    Publication Year: 2001 , Page(s): 3 - 5
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (349 KB) |  | HTML iconHTML  

    This paper describes the use of the multi-paradigms aspects of SystemC to develop hardware libraries, to reuse designs, to accelerate simulation, and to allow efficient design space exploration both at the RTL and architectural levels. Concepts of commonality and variation are used to compare SystemC capabilities to those of VHDL. View full abstract»

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  • Micro-machining of [100] Si using a novel ultra-violet induced anisotropic etching in HNA solution

    Publication Year: 2001 , Page(s): 91 - 94
    Cited by:  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (623 KB) |  | HTML iconHTML  

    Anisotropic etching of <100> silicon is achieved, for the first time, in the presence of ultra-violet exposure in a solution containing hydrofluoric/ nitric/ acetic acids (HNA). The HNA solution is regularly used for polishing silicon and etching polysilicon due to its isotropic etching property. In the technique proposed in this paper, called UV-HNA, the etching of silicon is enhanced in the direction determined by UV exposure. A mixture of HF/HNO3/HCOOH with a relative composition of 1:15:5 seems suitable for revealing [111] planes with an etch rate of 10 μm/hr at 35°C. Some anomalous behavior of etching in the presence of UV exposure is discussed. Bottom of the etched craters is hillock-free and etch rates as high as 60 μm/hr can be achieved using higher concentration of HF acid in HNA solution. In the latter case the etching is less anisotropic and mask undercut is observed. View full abstract»

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  • Fault diagnosis and fault localisation in integrated circuit by thermal method

    Publication Year: 2001 , Page(s): 230 - 233
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (429 KB) |  | HTML iconHTML  

    In the paper, a thermal testing method for integrated circuits (ICs) is presented. This method compares the real temperature field with the standard field, suitable for the specified energy state of the system. A method of temperature sensor placement strategy is presented as well. This placement method is proposed for fault diagnosis and fault localisation in ICs. An algorithm based on mutual dependencies of average temperatures of selected sub-areas of the IC in order to locate failure is described. Simulation results of the sensor placement strategy and fault diagnosis and localisation are presented. Statistical analyses of the yield of the testing method are shown. View full abstract»

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  • Dynamic signal model in the surface channel charge coupled devices

    Publication Year: 2001 , Page(s): 145 - 148
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (374 KB) |  | HTML iconHTML  

    The CCDs are used widely in special applications for very large scale integration (VLSI). In this paper, we have studied transfer charges coupled devices (CCDs) between adjacent MOS capacities under the control of an externally applied voltage. In order to show the role of the potential space inter-electrodes, a numerical program was developed and adapted to different CCD technologies. View full abstract»

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  • Fault detection in large AC machines

    Publication Year: 2001 , Page(s): 193 - 196
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (399 KB) |  | HTML iconHTML  

    The emerging techniques of artificial neural networks (ANNs) are applied to the problem of developing an artificial neural system capable of detecting interlayer faults in large AC machines using line-end coil voltage measurements. The proposed ANN system is a two-layer back propagation neural network, which is basically a classifier capable of recognizing data vectors buried in noise. The developed ANN system is fast to train and produced reliable fault detection and localization with noisy measurements. Furthermore, the proposed system needs neither data pre-processing nor feature extraction networks. View full abstract»

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  • A fast hardware co-specification and co-simulation methodology integrated in a H/S co-design platform

    Publication Year: 2001 , Page(s): 253 - 256
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (497 KB) |  | HTML iconHTML  

    This paper presents an approach to mix hardware models based on C++ library and HDL components (e.g. VHDL or Verilog) in the same design. The C++ software library is based on Cynlib from CynApps. The developing environment is integrated on a co-design tool called Picasso. The C foreign language interface of the well-known Modelsim simulator is used as a unified platform integration. View full abstract»

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  • Communication graph and timing configuration for virtual components

    Publication Year: 2001 , Page(s): 245 - 248
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (423 KB) |  | HTML iconHTML  

    SOC design requires connecting and integrating intellectual property (IP) and virtual components (VC) from various sources. Among factors limiting IP reuse is their communications and interface incompatibility. IP integrators do not need to know and to understand how an IP is implemented, but they need a simple model describing its communication behavior, in addition to physical interface spec and timing diagrams. In the first part of this paper, we present a graph model to describe the communication behavior of a component including its timing constraints and flexibility. This model abstracts the functionality of the component and its implementation. In the second part, we present a method for timing analysis and configuration based on the communication behavior graph. View full abstract»

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  • HDL-A based modeling of a current mode ADC

    Publication Year: 2001 , Page(s): 125 - 128
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (409 KB) |  | HTML iconHTML  

    Mixed-mode simulations are increasingly recognized as useful methods for the validation of mixed-signal circuits before going on fabrication. HDL-A is one of the useful hardware description language devoted for analog and mixed-signal circuits. This paper attempts to validate the conversion algorithm of a multi-slope self-calibrated analog-to-digital converter by means of HDL-A. We show, for the analog part of the structure, the agreement between modeling and experimental results. View full abstract»

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  • Low temperature polysilicon growth on glass suitable for TFT fabrication

    Publication Year: 2001 , Page(s): 79 - 82
    Cited by:  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (579 KB) |  | HTML iconHTML  

    Polysilicon films are grown on ordinary glass substrates at temperatures as low as 380°C using a novel ultraviolet assisted metal-induced-crystallization technique. The silicon films grown using this method are suitable for the fabrication of thin film transistors. Samples prepared, consist of 1500 Å of silicon film deposited on 1000 Å silicon nitride and 2000 Å of chromium layers, and Ni is used as the seed for crystallization. Annealing occurred in the presence of an ultra-violet exposure and led to a high crystallinity silicon film as examined using XRD and SEM. The lateral growth as the main feature of this technique is presented using optical microscopy analysis. The preliminary results of transistor fabrication on ordinary glass is reported. Transistors fabricated using this technique show a hole mobility of 50 cm2/Vs. View full abstract»

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  • Characterization and modelling of nano-crystals for single electron memory point devices

    Publication Year: 2001 , Page(s): 39 - 42
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (468 KB) |  | HTML iconHTML  

    This paper presents some experimental results and a simple model for the study of capacitors containing silicon dots in silicon dioxide to be integrated in a new generation of nonvolatile single electron memories. This work is essential for the stabilisation of the technology to be used in the future for these devices aimed at very high memory arrays. View full abstract»

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  • Noise characterisation in CMOS APS imagers for highly integrated imaging systems

    Publication Year: 2001 , Page(s): 31 - 34
    Cited by:  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (362 KB) |  | HTML iconHTML  

    The design of active pixel image sensors (APS) fabricated in traditional CMOS foundries has been a topic of renewed interest in the last several years. The noise reduction is a key issue and often defines the sensitivity or detection limit. In this paper, a thorough noise analysis is made of the expected performance of the APS imagers. White noise and low-frequency (LF) noise sets a fundamental limit on APS performance, especially for low-light applications. Therefore, a detailed theoretical analysis of the in-pixel amplifier and the readout circuit response to the LF noise is investigated. Some experimental LF noise results obtained at room temperature on N-channel MOSFETs fabricated using a 0.7 μm CMOS process are presented. We show that the LF noise spectra generated by small area MOSFETs are Lorentzian rather than pure 1/f shape chiefly for the weak inversion mode. Next, using PSPICE simulations, the noise due to the readout circuit during integration is carried out. View full abstract»

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  • Graphics acceleration of composite transformations using reconfigurable computing

    Publication Year: 2001 , Page(s): 226 - 229
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (563 KB) |  | HTML iconHTML  

    This paper introduces reconfigurable computing (RC) and specifically chooses one of the prototypes in this field, MorphoSys (M1) from UCI. Mapping of different linear algebraic functions, namely vector-scalar operations, onto this hardware is proposed. A performance analysis study of the M1 RC is also presented to evaluate the efficiency of the algorithm execution on the M1 system. For instance, two algorithms on an 8×8 RC array M1 were run, and numerical examples were simulated to validate our results, using the MorphoSys mULATE program, which simulates MorphoSys operations. View full abstract»

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  • Conception of single-lithography and space technologies of ULSI and WSI on functional nanoelectronic and optoelectronic elements

    Publication Year: 2001 , Page(s): 95 - 98
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (471 KB) |  | HTML iconHTML  

    Dynamics and reforms by which the semiconductor industry could be transformed into next-generation manufacturing of Si deep-submicron and nanoelectronic ULSI and WSI are discussed For competitive Si ULSI and WSI the functional integration becomes a core design principle and cardinal simplification of manufacturing processes/equipment becomes a core technology principle. Concept of global single lithography (no-lithography on spacefab) technology for nanoelectronic complementary bipolar field-effect (CBFE), Vertical Merged MOS (VMMOS) and optoelectronic VMMOS (OVMMOS) increasing the packaging density for high-speed low-voltage ULSI and WSI is considered Technology and economics (Technonomics) concepts of space hyperhigh- vacuum technologies and processing in framework of flexible scalable no-lithography spacefab under condition of orbital flight are presented. View full abstract»

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