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Microelectronics, 2001. ICM 2001 Proceedings. The 13th International Conference on

Date 29-31 Oct. 2001

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Displaying Results 1 - 25 of 67
  • Microelectronics to build smart medical devices

    Publication Year: 2001
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (191 KB)  

    Summary form only given. The bladder controller and the visual cortical stimulator are the main subjects of research activities of the PolySTIM team at the Ecole Polytechnique de Montreal. Such devices are dedicated to recuperate or enhance neuromuscular functions in patients by means of peripherals or central nervous systems. While the bladder controllor is dedicated to recuperate voiding and retention functions on paralyzed patients, the electronic visual stimulator is dedicated to create adequate vision for totally blind patients. Neural peripheral sacral stimulation is applied to recover the bladder function, but direct stimulation of the brain is the basic principle of the visual cortex stimulator proposed by PolySTIM. The author elaborates the design and validation of the visual implant that involves an advanced stimulator mounted on a matrix of 25×25 microelectrodes which are implanted on the visuel cortex to recover partial vision for blind patients. View full abstract»

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  • Dynamic signal model in the surface channel charge coupled devices

    Publication Year: 2001 , Page(s): 145 - 148
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (374 KB) |  | HTML iconHTML  

    The CCDs are used widely in special applications for very large scale integration (VLSI). In this paper, we have studied transfer charges coupled devices (CCDs) between adjacent MOS capacities under the control of an externally applied voltage. In order to show the role of the potential space inter-electrodes, a numerical program was developed and adapted to different CCD technologies. View full abstract»

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  • HDL-A based modeling of a current mode ADC

    Publication Year: 2001 , Page(s): 125 - 128
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (409 KB) |  | HTML iconHTML  

    Mixed-mode simulations are increasingly recognized as useful methods for the validation of mixed-signal circuits before going on fabrication. HDL-A is one of the useful hardware description language devoted for analog and mixed-signal circuits. This paper attempts to validate the conversion algorithm of a multi-slope self-calibrated analog-to-digital converter by means of HDL-A. We show, for the analog part of the structure, the agreement between modeling and experimental results. View full abstract»

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  • Design and characterization of a monolithic amplifier for millimeter wave

    Publication Year: 2001 , Page(s): 177 - 180
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (369 KB) |  | HTML iconHTML  

    This paper focuses on design and characterization of integrated circuits working in the millimeter wave. The circuit consists of a monolithic amplifier, aimed for wireless indoor communications at 60 GHz. A calibration kit has also been developed in order to perform proper measurement on wafer. View full abstract»

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  • An original buffer circuit for medium and high-power applications

    Publication Year: 2001 , Page(s): 173 - 176
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (445 KB) |  | HTML iconHTML  

    We present the dc characteristics of a an output stage and buffer circuit for medium to high-power applications that provides near optimal performance over a wide range of power levels and frequencies, while avoiding the use of output feedback resistors and/or thermistors for thermal compensation. The circuit uses a complementary emitter follower that operates in class-AB mode, with identical matched devices used in the bias and output stages. It provides an excellent impedance conversion between the input and output stages. For instance the load decoupling is greater than 45 dB for a circuit that uses the Tip29,30 standard complementary transistor pair. Also, the power transmission efficiency between the source and the load is maximized without the usual losses and/or distortions. View full abstract»

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  • Theoretical modeling of PtSi/porous Schottky detectors

    Publication Year: 2001 , Page(s): 47 - 49
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (417 KB)  

    The current-voltage characteristic of PtSi/porous Si Schottky detectors has been modeled. It is assumed that high electric fields are developed at sharp and irregular edges of the porous surface, causing avalanche and tunneling breakdown. The shape of the I-V curve, its change with temperature, its response to near and far IR, and the large quantum efficiency are satisfactorily explained by this model. View full abstract»

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  • Lateral plasma display panels suitable for fabrication on flexible substrates

    Publication Year: 2001 , Page(s): 83 - 86
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (612 KB) |  | HTML iconHTML  

    A pixel structure is proposed, for the first time, which is suitable for the fabrication of plasma display panels on flexible substrates such as stainless foils and PET. In this approach, the plasma is generated laterally between two electrodes. The positive and negative electrodes are realized on a single substrate and their spacing is adjusted by photolithography, so that exploiting a rigid substrate is no longer a necessity. The distance between the electrodes is not varied during substrate warping and hence fabrication of a flexible PDP is feasible. The conversion of ultra-violet light into visible color is feasible by using phosphorescent coatings. Also the structure used in this approach does not need transparent conductors like ITO. The isolation of the electrodes is possible by a silicon-oxide layer deposited using a liquid phase deposition (LPD). Also, the metallic electrodes can be realized using electroless plating suitable for large area fabrication. View full abstract»

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  • A 3.3 V high-resolution sigma-delta modulator for digital audio

    Publication Year: 2001 , Page(s): 129 - 132
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (358 KB)  

    This paper discusses the architecture and circuit requirements for a CMOS sigma-delta modulator that provides digital audio performance. The performance objective is to achieve a dynamic range of 110 dB (18-bit resolution) for a 25 kHz signal bandwidth while operating from a single 3.3 V power supply. View full abstract»

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  • Estimation and optimization of delay in popular CMOS logic styles

    Publication Year: 2001 , Page(s): 50 - 53
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (470 KB) |  | HTML iconHTML  

    This paper presents a unified model for delay estimation in various CMOS logic styles. It also derives closed-form optimal transistor sizing formulas for minimizing the delay in each logic style. The paper demonstrates the use of these formulas for delay optimization in mixed logic-style CMOS circuits. Mixing CMOS logic styles in a circuit has the potential of improving performance and reducing energy dissipation and area. View full abstract»

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  • Electroluminescence analysis of neutron irradiation of JFETs

    Publication Year: 2001 , Page(s): 71 - 74
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (333 KB) |  | HTML iconHTML  

    Electroluminescence (EL) measurements are used as a sensitive technique for the study of fast neutron irradiation of silicon n-channel JFET overlaid by a passivation oxide layer. By theoretical simulations, it is demonstrated that neutron irradiation result in two effects: an increase of the refractive index of the passivation oxide and the introduction of deep level traps which reduce the emitted intensities by reduction of the mobility of hot carriers. View full abstract»

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  • Design and verification of an ATM Knockout switch concentrator

    Publication Year: 2001 , Page(s): 261 - 264
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (463 KB) |  | HTML iconHTML  

    In this paper we describe the design and verification of the concentrator of a Knockout ATM (Asynchronous Transfer Mode) switch fabric using the VIS tool. The Knockout is a popular ATM switch fabric which has application in both datagram and virtual circuit packet networks. The concentrator is the most difficult component in the Knockout ATM switch fabric. We developed an RTL structural design as well as a higher-level behavioral model of the Knockout switch concentrator in Verilog HDL. We then used equivalence checking within VIS to verify the concentrator structure against its behavioral model. While sequential equivalence checking failed, we succeeded the combinational equivalence checking of a latch-reduced model of the concentrator. View full abstract»

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  • Miniaturized SnO2-based suitable for temperature-tailored lambda-ratio sensors

    Publication Year: 2001 , Page(s): 87 - 90
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (634 KB) |  | HTML iconHTML  

    A sol-gel method for the fabrication of miniaturized SnO2 sensors, compatible with Si technology, is described. The fabrication procedure consists of deposition and patterning of Pt heating elements and sensor contact pads. The SnO2 sensing element is formed through a new sol-gel method exploiting a lift-off step for patterning. Sintering of the sensor at a temperature of 600°C finalizes the fabrication. Preliminary results of sensor characteristics are reported. In addition, the behaviour of SnO2 sensors fabricated using a pressed-pallet method with anomalous characteristics is addressed. The temperature-dependent response of SnO2-based sensors as a λ-ratio sensing device is reported. A low-high transition in the sensor conductivity, occurring at a ratio of combustible to oxygen gases away from the stoichiometric value, is reported for the first time. The ratio at which this transition arises, happens at values higher than the stoichiometric point for CO and by raising the temperature, it moves towards the stoichiometric point. This phenomenon is reversed for C2H6. View full abstract»

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  • A polynomial division pipelined architecture for CRC error detecting codes

    Publication Year: 2001 , Page(s): 133 - 136
    Cited by:  Patents (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (394 KB) |  | HTML iconHTML  

    Error detection in telecommunication applications is frequently ensured with CRC (Cyclic Redundancy Checking). However, the evolution towards increasing data rates increases the need for more and more sophisticated implementations. In this paper, we present an effective architecture for the CRC function based on a pipelined implementation of the polynomial division. It improves very effectively the speed performance, allowing data rates from 1 Gbit/s to 4 Gbit/s on FPGA implementations, according to the parallelisation level (8 to 32 bit). View full abstract»

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  • FPGA-based IC design for inverter with vector modulation technique

    Publication Year: 2001 , Page(s): 185 - 188
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (395 KB) |  | HTML iconHTML  

    Presents an application of a Xilinx FPGA device, in the CX4000 family, producing pulse width modulation (PWM) signals with the vector modulation technique for an IGBT inverter. Using a single FPGA chip for the practical implementation of the modulator, rather than a system consisting of microprocessor and external memory, has many advantages including less use of power and space, short design time, greater speed and reliability. The designed circuit can generate PWM signals, and also, the input values used to adjust output signal may be obtained through a microprocessor port. A comparison between the implementation on DSP and on FPGA at the level time will be made to validate the use of the FPGA. View full abstract»

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  • Fault location in distribution networks using clustering techniques

    Publication Year: 2001 , Page(s): 197 - 202bis
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (506 KB) |  | HTML iconHTML  

    This paper studies an existing 13.8 kilovolt distribution network which serves an oil production field spread over an area of approximately sixty kilometers square, in order to locate any fault that may occur anywhere in the network using fuzzy c-mean classification techniques. In addition, the paper introduces several methods for normalizing data and selecting the optimum number of clusters in order to classify data. Results and conclusions are given to indicate the feasibility of the suggested fault location method. View full abstract»

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  • Noise characterisation in CMOS APS imagers for highly integrated imaging systems

    Publication Year: 2001 , Page(s): 31 - 34
    Cited by:  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (362 KB) |  | HTML iconHTML  

    The design of active pixel image sensors (APS) fabricated in traditional CMOS foundries has been a topic of renewed interest in the last several years. The noise reduction is a key issue and often defines the sensitivity or detection limit. In this paper, a thorough noise analysis is made of the expected performance of the APS imagers. White noise and low-frequency (LF) noise sets a fundamental limit on APS performance, especially for low-light applications. Therefore, a detailed theoretical analysis of the in-pixel amplifier and the readout circuit response to the LF noise is investigated. Some experimental LF noise results obtained at room temperature on N-channel MOSFETs fabricated using a 0.7 μm CMOS process are presented. We show that the LF noise spectra generated by small area MOSFETs are Lorentzian rather than pure 1/f shape chiefly for the weak inversion mode. Next, using PSPICE simulations, the noise due to the readout circuit during integration is carried out. View full abstract»

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  • Fault detection in large AC machines

    Publication Year: 2001 , Page(s): 193 - 196
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (399 KB) |  | HTML iconHTML  

    The emerging techniques of artificial neural networks (ANNs) are applied to the problem of developing an artificial neural system capable of detecting interlayer faults in large AC machines using line-end coil voltage measurements. The proposed ANN system is a two-layer back propagation neural network, which is basically a classifier capable of recognizing data vectors buried in noise. The developed ANN system is fast to train and produced reliable fault detection and localization with noisy measurements. Furthermore, the proposed system needs neither data pre-processing nor feature extraction networks. View full abstract»

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  • A sub-0.5 V dynamic threshold PMOS (DTPMOS) scheme for bulk CMOS technologies

    Publication Year: 2001 , Page(s): 75 - 78
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (371 KB) |  | HTML iconHTML  

    A new dynamic threshold PMOS (DTPMOS) scheme is presented. In this scheme, the gate of a PMOS transistor is connected to its well in a conventional bulk CMOS technology. This technique results in improved switching speed compared to conventional CMOS in the sub-0.5 V regime. A 32-bit carry skip adder is designed for low voltage, low energy applications using the DTPMOS scheme. This adder consumes only 0.25 pJ of energy at a frequency of 5 MHz. The proposed design results in a 64% reduction in delay and 26% saving in energy compared to the conventional CMOS implementation. View full abstract»

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  • E-commerce new trends: Virtual Design Support Center (VDSC)

    Publication Year: 2001 , Page(s): 265 - 268
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (437 KB) |  | HTML iconHTML  

    Learning on-line is one of the fastest moving trends in higher education as engineers and executives in technology industries are discovering. Today, thanks to the widespread access to the Internet, on-line education is enabling professional for continues learning and keeping pace with technological and managerial changes despite their heavy schedule. In this paper we will discuss the importance of E-learning in electronics technology as well as the need for the Virtual Design Support Center (VDSC). View full abstract»

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  • Micro-machining of [100] Si using a novel ultra-violet induced anisotropic etching in HNA solution

    Publication Year: 2001 , Page(s): 91 - 94
    Cited by:  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (623 KB) |  | HTML iconHTML  

    Anisotropic etching of <100> silicon is achieved, for the first time, in the presence of ultra-violet exposure in a solution containing hydrofluoric/ nitric/ acetic acids (HNA). The HNA solution is regularly used for polishing silicon and etching polysilicon due to its isotropic etching property. In the technique proposed in this paper, called UV-HNA, the etching of silicon is enhanced in the direction determined by UV exposure. A mixture of HF/HNO3/HCOOH with a relative composition of 1:15:5 seems suitable for revealing [111] planes with an etch rate of 10 μm/hr at 35°C. Some anomalous behavior of etching in the presence of UV exposure is discussed. Bottom of the etched craters is hillock-free and etch rates as high as 60 μm/hr can be achieved using higher concentration of HF acid in HNA solution. In the latter case the etching is less anisotropic and mask undercut is observed. View full abstract»

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  • CAD flow for system on chip

    Publication Year: 2001 , Page(s): 241 - 244
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (419 KB) |  | HTML iconHTML  

    The introduction of very high deep sub-micron technology introduces a lot of new problems due to the increase in complexity. In order to handle huge chips containing 40-50 millions of transistors gathered in 30-40 blocks (commonly named IPs), multi clock domains, multi powered analog blocks, routed on 6 metal layers with some wire length measuring up to 3 cm, a hierarchical approach must be set up focusing on verification and timing closure. The author considers the following aspects of the problem: timing, data structures, top-down methodology, design teams, RTL quality, logic design standardization, DFT rules, formal proof, system verification, timing block level sign-off, and physical sign-off. View full abstract»

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  • CMP provides the access to advanced low cost manufacturing

    Publication Year: 2001 , Page(s): 20 - 24
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (484 KB) |  | HTML iconHTML  

    CMP aims at providing universities, research laboratories and industries with the possibility of having their integrated circuit projects fabricated for prototyping and low volume production. Presently, users are serviced for CMOS double layer poly/double layer metal (DLP/DLM) 0.8 μm, DLM/TLM 0.6 μm, DLP/4LM 0.35 μm, SLP/6LM 0.25 μm, SLP/6LM 0.18 μm, BiCMOS DLP/DLM 0.8 μm, SiGe HBT 0.8 μm DLP/DLM, SiGe HBT 0.35 μm SLP/5LM and GaAs HEMT 0.2 μm. About 40 multi-project runs are offered per year. Micro Electro Mechanical Systems (MEMS) are also provided in standard CMP runs in CMOS DLP/DLM 0.8 μm and 0.6 μm, BiCMOS DLP/DLM 0.8 μm and HEMT GaAs 0.2 μm, using compatible front-side bulk micro-machining. MUMPS is offered as a surface micro-machining process, allowing one to integrate MEMS only microstructures. Finally, the main processes for Multi-Chip Modules (MCMs) are also available through CMP. View full abstract»

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  • Differential injection analysis based on backside-contacted ISFETs

    Publication Year: 2001 , Page(s): 119 - 122
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (535 KB) |  | HTML iconHTML  

    In this paper a differential injection analysis (DIA) based on ISFETs is presented. The method consists of differential measurements in two parallel micro-cells with identical ISFET sensors connected in the output port. Sample is injected in the first cell as in conventional FIA systems, while in the second cell it is injected as reference buffer. In this way, a simple method for differential measurements is implemented avoiding the need of a reference electrode. By using BSC-ISFET technology integrated with tubular microcell, parallel cells with identical ISFETs are obtained in batch-fabrication. View full abstract»

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  • Multimedia multi-challenges

    Publication Year: 2001 , Page(s): 6 - 10
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (478 KB) |  | HTML iconHTML  

    The author describes the impact of multimedia on the microelectronics industry, particularly the integration of the "old" segments: computer, consumer, telecommunication, and automotive. Semiconductor companies have been obliged to integrate complete systems on chips and to develop software, leaving most of the traditional silicon design problems to the EDA community at least for the digital portions. Some examples are presented, including pocket multimedia. View full abstract»

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  • Power bus optimal sizing in presence of power supply noise

    Publication Year: 2001 , Page(s): 111 - 114
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (522 KB) |  | HTML iconHTML  

    As a consequence of the growing complexity in ultra deep submicron designs, phenomena like IR drops, electromigration and ground bounce are assuming increasing proportions in high performance integrated circuits, compromising their performances and their functionality. This paper suggests a methodology to evaluate power supply noise generation while optimizing power supply bus sizes. Its appropriateness seems to be helpful if applied during the circuit design flow in conjunction with a project tool having as a preeminent target noise reduction. View full abstract»

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