By Topic

Quality Electronic Design, 2002. Proceedings. International Symposium on

Date 21-21 March 2002

Filter Results

Displaying Results 1 - 25 of 87
  • Proceedings International Symposium on Quality Electronic Design

    Publication Year: 2002
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (401 KB)  

    The following topics are dealt with: interconnect extraction and modeling; design for process variations; design issues for power and noise management; low power design techniques; quality and interoperability of EDA tools; power, signal and EMI analysis and optimization; verification in achieving design quality; advanced device technology issues in circuit design; design for test; methods and metrics for design quality; signal integrity; design, planning and closure. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient closed-form crosstalk delay metrics

    Publication Year: 2002 , Page(s): 431 - 436
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (249 KB) |  | HTML iconHTML  

    In this paper we present efficient closed-form formulas to estimate capacitive coupling-induced delay in distributed RC coupling network. The efficiency of our approach stems from the fact that only five basic operations are used in the expressions: addition, subtraction, multiplication, division, and square root. The formulas do not require exponent computation or numerical iterations. Our estimates are conservative, and yet achieve acceptable accuracy. They are simple enough to be used in the inner loops of performance optimization or as cost functions for a router. The delay expressions capture the dependency on coupling direction and coupling location. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Author index

    Publication Year: 2002 , Page(s): 539 - 541
    Save to Project icon | Request Permissions | PDF file iconPDF (250 KB)  
    Freely Available from IEEE
  • Transition aware global signaling (TAGS)

    Publication Year: 2002 , Page(s): 53 - 59
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (282 KB) |  | HTML iconHTML  

    We propose a new receiver to reduce the number of repeaters used in global wiring. The receiver stores the next state of the line while quiet. Upon detection of a transition at the end of the line the output is temporarily driven by the stored next state. Transitions at the output of the receiver are much faster than at the end of the line since they are generated locally. Using the TAGS receiver we can run a 15 mm line (180 nm node) at 800 MHz with no repeaters. The same line requires three repeaters with a traditional receiver and consumed more power and area. The TAGS receiver also outperforms a standard inverter at the 70 nm technology node. A noise analysis at the two technology nodes shows that the receiver maintains good functional noise immunity. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Using the Open Library Architecture (OLA) open source API in heterogeneous design flows

    Publication Year: 2002 , Page(s): 63 - 68
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (237 KB) |  | HTML iconHTML  

    Design and timing closure are critical issues in modern design flows. Industry common library formats like .lib, CLF and TLF do not provide a means to embed arbitrary delay information and complex interconnect algorithms. Designers and silicon providers are at the mercy of these restrictions. Algorithms are applied to characterization data and proprietary interconnect analysis modules to minimize the error when mapping into these formats. The result is that numerous errors creep in to the tools that employ these formats. Often, these inaccuracies force unnecessary design iterations, technology guard banding, and finger pointing between the tool and library providers. With interconnect delay dominating path timing, it is more critical than ever to move past the text based library formats and to an API based solution that provides a way to embed interconnect analysis in the technology models. The Open Library Architecture addresses these issues by implementing an open C API. This API allows the library vendor to implement arbitrary data structures and algorithms. The same OLA module is employed consistently throughout the design flow which eliminates the loops which lead to inaccurate library mapping algorithms. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Inductive characteristics of power distribution grids in high speed integrated circuits

    Publication Year: 2002 , Page(s): 316 - 321
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (289 KB) |  | HTML iconHTML  

    The inductive characteristics of several types of gridded power distribution networks are described in this paper. The inductance extraction program FastHenry is used to evaluate the inductive properties of grid structured interconnect. In power distribution grids with alternating power and ground lines, the inductance is shown to vary linearly with grid length and inversely linearly with the number of lines in the grid. The inductance is also relatively constant with frequency in these grid structures. These properties provide accurate and efficient estimates of the inductance of power grid structures with various dimensions. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Noise injection and propagation in high performance designs

    Publication Year: 2002 , Page(s): 425 - 430
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (246 KB) |  | HTML iconHTML  

    Signal integrity has become a critical issue in the design of high-performance circuits. Noise on a net arises both through propagation of noise from previous stages through the driver gate of the net and through injection of new noise through coupling capacitance with neighboring nets. Typically, propagated noise and injected noise are added linearly to simplify the analysis and increase its efficiency. In this paper, we show that this linear assumption results in a significant underestimation of the noise, due to the nonlinear behavior of the driver gate, and hence can lead to many undetected noise failures in the design. Since complete nonlinear simulation is too slow for large cell-based designs, we propose a new linear model that accurately captures the nonlinear behavior of the driver gate. We propose three iterative methods for computing the model parameters of this linear model. Results are presented to demonstrate the accuracy of the proposed approach on several industrial designs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The OpenAccess coalition - the drive to an open industry standard information model, API, and reference implementation for IC design data

    Publication Year: 2002 , Page(s): 69 - 74
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB) |  | HTML iconHTML  

    The rapidly increasing complexity of integrated circuit design can only be addressed effectively by a design system architecture that supports very efficient, high-quality sharing of IC design data. Integration of the wide variety of tools required to design and verify the performance and quality of ICs can no longer depend on low-bandwidth file formats. Rather, an application programming interface (API) to a standard information model (IM) that provides access to a shared database is an essential infrastructure component of today's IC design systems. Furthermore, this design data API should be standard across the IC CAD industry so that design systems can efficiently draw from best-of-class applications from all sources in the EDA industry. The tight coupling of all tools through a common IM/API enables rapid design convergence with an earlier emphasis on quality issues, which results in higher quality ICs while meeting aggressive time-to-market demands. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Characterizing the current degradation of abnormally structured MOS transistors using a 3D Poisson solver

    Publication Year: 2002 , Page(s): 322 - 325
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB) |  | HTML iconHTML  

    An efficient modeling methodology for abnormally structured MOS transistors is presented. Contrary to the previous method utilizing a 3D device simulator, only the 3D Poisson solver is used to characterize the current degradation effects by extracting the parasitic source and drain resistances, and the effective transistor width of the abnormal transistors. For the frequent modifications of the layout design, the easiness of the proposed method guarantees the efficient reflection of the current degradation effect in circuit simulation. This method is applied to 0.17 μm DRAM process and the good agreements with the measured data are examined. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Productivity optimization techniques for the proactive semiconductor manufacturer

    Publication Year: 2002
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (174 KB)  

    Summary form only given. The experienced semiconductor manufacturer is often confronted by apparently similar products that yield drastically different productivities. The same processes are used to fabricate these chips, yet the manufacturer's costs are clearly different. The customers expect similar pricing and a deviation must be accompanied by a credible explanation. Design for manufacturability (DFM) has become a popular industry term, yet many chip designers are uncertain where to start and what to implement. The semiconductor manufacturer possesses knowledge or suspicions of potential barriers and improvement opportunities. This information must be proactively fed forward to the design shops, which must also budget resources and time to address these items. This presentation describes how this process works, illustrated with examples from IBM Microelectronics' Vermont facility. Before focusing on productivity optimization, a recommended set of metrics is identified, and the concept of physical design characterization is overviewed. Past and existing designs provide excellent historical insight into a large number of issues that are often independent of technology node. While robust technology development objectives strive to minimize the potential manufacturing stumbling blocks, competitive pressures will balance these with other constraints. Ultimately, it is decisions made by a designer that will determine the level of productivity achievable. Much of this presentation is devoted to describing a number of these decisions. In addition, the manufacturer may deploy complex algorithms to adjust the design to process constraints. Another, but more costly solution is for the manufacturer to tailor the process to a specific product, compensating for identified product-technology gaps. Lastly, this presentation ties these concepts together into a recommended business process. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • ALBORZ: Address Level Bus Power Optimization

    Publication Year: 2002 , Page(s): 470 - 475
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (271 KB) |  | HTML iconHTML  

    In this paper we introduce a new low power address bus encoding technique, and the resulting code, named ALBORZ. The ALBORZ code is constructed based on transition signaling the limited-weight codes and, with enhancements to make it adaptive and irredundant, results in up to 89% reduction in the instruction bus switching activity, at the expense of a small area overhead. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A qualification platform for design reuse

    Publication Year: 2002 , Page(s): 75 - 80
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3259 KB) |  | HTML iconHTML  

    The application and development of reusable components (intellectual property, IP) has become a regular part of modern design practices. The IP provider on one side and the IP integrator (user) on the other may be in the same company or separate participants in the microelectronic design market. In both cases, the transfer of IP remains a complex and time-consuming task. The qualification of IP gains a significant relevance for successful application and transfer of IP. This paper proposes an IP qualification methodology for an automated quality check that also incorporates current standards. Through embedding of the new concept into the regular design flow, IP transfer comes closer to an easy mix and match of virtual components. The presented approach has been validated during an industrial case study. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Test generation and fault modeling for stress testing

    Publication Year: 2002 , Page(s): 95 - 99
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (245 KB) |  | HTML iconHTML  

    Voltage stress testing has long been used as a reliability screen. Significant effort has been devoted in the reliability physics literature to setting of stress voltages. Chang and McCluskey formalized the test aspects of voltage stressing in their works on "SHOVE (SHort VOltage Elevation)" testing. Their work deals with 3.3V and 5V technologies where Fowler-Nordheim tunneling is dominant and suggests a stress energy of about 6MV/cm. In current generation technologies, Fowler-Nordheim tunneling is replaced by standard tunneling currents and operating energies are in the suggested stress range (e.g. 1.2V power supply with a 20Å oxide is 6MV/cm). Modified methods are developed to support this new situation, and a rest generation technique is introduced that enables substantial reduction in the number of stress vectors. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new design cost model for the 2001 ITRS

    Publication Year: 2002 , Page(s): 190 - 193
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (211 KB) |  | HTML iconHTML  

    The International Technology Roadmap for Semiconductors (ITRS) presents an industrywide consensus on the "best current estimate" of the industry's research and development needs out to a 15-year horizon. As such, it provides a guide to the efforts of companies, research organizations, and governments. The ITRS has improved the quality of R&D investment decisions made at all levels and has helped channel research efforts to areas that truly need research breakthroughs. The 2001 edition of ITRS is the result of a worldwide consensus building process. The participation of semiconductor experts from Europe, Japan, Korea, Taiwan, and the USA. has ensured that the 2001 ITRS continues to be the definitive source of guidance for semiconductor research as we strive to extend the historical advancement of semiconductor technology. This paper presents details of an important new element of the 2001 ITRS, namely, the design cost model that has been introduced in the design chapter. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Trends in low power digital system-on-chip designs

    Publication Year: 2002 , Page(s): 373 - 378
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (261 KB) |  | HTML iconHTML  

    A study of the future trends in low-power System-on-Chip (SoC) designs is presented, based on the recently announced ITRS-2001 technology characteristics for both high-performance and low-power devices from 2001 to 2016. We forecast the logic/memory composition of a reference low-power PDA design with an area constraint of 1 cm2 using both a bottom-up, power dissipation-constrained chip model and a top-down, design resource-constrained model. Together, these analyses indicate that without accelerated improvements in both chip design productivity and leakage power management, future SoC designs will be comprised of 80-90% memory, with the remaining logic blocks composed of special-purpose reusable IP cores, and a smaller fraction of the chip containing newly designed logic. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimal sequencing energy allocation for CMOS integrated systems

    Publication Year: 2002 , Page(s): 194 - 199
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (403 KB) |  | HTML iconHTML  

    All synchronous CMOS integrated systems have to pay some sequencing overhead. This overhead includes the skew and the jitter of the clock. It also includes the setup time and the clock-to-output delay of the flip-flops. This paper discusses how much energy should be allocated for sequencing in these systems. It is pointed out that providing too little energy is just as bad as providing too much. It is also argued that directly trying to minimize the energy-delay product of the sequencing subsystem is practically not the right thing to do. A model for the relationship between supply voltage, clock frequency, and power dissipation is developed and empirically verified for a SPARC V9 microprocessor. An expression for the optimal energy allocation in a system is derived. Then, based on this optimum, a methodology to design energy-efficient systems is proposed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • False-noise analysis using resolution method

    Publication Year: 2002 , Page(s): 437 - 442
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (237 KB) |  | HTML iconHTML  

    High-performance digital circuits are facing increasingly severe noise problems due to cross-coupled noise injection. Traditionally, noise analysis tools use the conservative assumption that all neighbors of a net can switch simultaneously, thereby producing the worst-case noise on a net. However, due to the logic correlations in the circuit, this worst-case noise may not be realizable, resulting in a so-called false noise failure. Since the problem has been shown to be NP-hard in general, exact solutions to this problem are not possible. In this paper, we therefore propose a new heuristic to eliminate false noise failures based on the resolution method. It is shown that multi-variable logic relations can be computed directly from a transistor level description. Based on these generated logic relations, a characteristic ROBDD for a signal net and its neighboring nets is constructed. This ROBDD is then used to determine the set of neighboring nets that result in the maximum realizable noise on the net. The proposed approach was implemented and tested on industrial circuits. The results demonstrate the effectiveness of the approach to eliminate false noise failures. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Advancing quality of EDA software

    Publication Year: 2002 , Page(s): 81 - 86
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (276 KB) |  | HTML iconHTML  

    In the fast-paced electronics market, design engineers face incredible challenges to keep up with increasing technology complexity and time-to market pressures. Under these challenges, design engineers have been saying that quality issues with their EDA software tools cost them dearly in lost productivity and in missing tight deadlines. Therefore, improving the quality of EDA software tools and processes is essential to the designers' success. Our paper describes a proven methodology for implementation of an effective quality management system (QMS) for driving quality improvements in the EDA industry. The paper provide real-life examples of how this quality management system contributed to improvements in the quality of many EDA software tools that were developed by a leading EDA tool supplier. The positive results of the software process improvement effort demonstrated that investing in quality does pay. Effective implementation of the quality management system described in this paper has reduced software bugs and defects, produced improvements in meeting commitments, and contributed to the overall increase in customer satisfaction. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Megagate ASICs for the Thuraya satellite digital signal processor

    Publication Year: 2002 , Page(s): 479 - 486
    Cited by:  Papers (2)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (422 KB) |  | HTML iconHTML  

    Boeing Satellite Systems and IBM have designed and fabricated a, set of ASIC chip types to perform computation-intensive digital signal processing (DSP) functions on board geosynchronous satellites of the Thuraya mobile communications system. Preparation for this application required comprehensive review of the reliability and space-worthiness of the underlying process and packaging technology. First-pass success on all nine million-plus-gate ASIC designs required extensive model-based simulation and verification. These technologies allowed a four-fold increase in the computational power of the DSP unit over previous systems based on radiation-hardened ASICs, while simultaneously decreasing the number of ASICs required by another factor of five. The first Thuraya satellite is on-orhit, and the whole communications system is performing flawlessly. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Extending the viability of IDDQ testing in the deep submicron era

    Publication Year: 2002 , Page(s): 100 - 105
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (298 KB) |  | HTML iconHTML  

    IDDQ testing has become a widely accepted defect detection technique in CMOS ICs. However, its effectiveness in deep submicron is threatened by the increased transistor sub-threshold leakage current. In this paper, a new IDDQ testing scheme is proposed. This scheme is based on the elimination, during IDDQ testing, of the normal leakage current from the sensing node of the circuit under test so that already known in the open literature IDDQ sensing techniques can be applied in deep submicron. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Wireless systems-on-a-chip design

    Publication Year: 2002
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (304 KB)  

    Summary form only given. There is a fundamental shift that is occurring in the implementation of wireless systems. Not only is the underlying technology shifting to mainstream CMOS technology, but the applications and specifications of the supported links are also rapidly evolving. The multiple inter-related technologies required for implementation of such wireless systems requires a co-design strategy in communication algorithms, digital architectures and the analog and digital circuits required for their implementation. Critical to good design of these chips is the definition of energy and area performance metrics that can facilitate the tradeoff of issues such as the cost of providing flexibility or the amount of parallelism to exploit. These design decisions can result in differences of orders of magnitude in the metrics between what is possible in the technology and what is often achieved if the costs are not fully understood. A design infrastructure which supports architectures and which optimizes the metrics is described for wireless systems, providing a fully automated chip design flow from a high level system specification. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An EMI-noise analysis on LSI design with impedance estimation

    Publication Year: 2002 , Page(s): 169 - 174
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (294 KB) |  | HTML iconHTML  

    The EMI noise of LSI has become more significant factor for LSI reliability. The result of a transistor-level simulator was not compared sufficiently with measurement and needs the final layout. This paper shows an EMI-noise analysis method at the early stage of the LSI design. The spectrum of the power supply current and the frequency response of the LSI estimated impedance are merged analytically at high speed. The current can be calculated at high speed by a gate level simulator with a triangle model. The experimental results show that our method has a high accuracy that is correlated with measurement results. Furthermore, the estimation method of the LSI impedance enables EMI noise prediction at the early stage of LSI design. The information obtained from our method can also help designers to improve LSI and electronic systems design quality. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low-power and high-speed V VLSI design with low supply voltage through cooperation between levels

    Publication Year: 2002 , Page(s): 445 - 450
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1551 KB) |  | HTML iconHTML  

    In this paper, methods to achieve low-power and high-speed VLSI's are described with the emphasis on cooperation between levels. To suppress the leakage current in a standby mode, Boosted Gate MOS (BGMOS) is effective, which is based on cooperation between technology level and circuit level. To reduce the power in an active mode, VDD-hopping and VTH-hopping are promising, which are cooperative approaches between circuit and software. The power consumed in an interconnect system is another issue in low-voltage deep-submicron designs. A cooperative approach between VLSI and assembly to the interconnect power problem is also discussed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fabrication technologies for three-dimensional integrated circuits

    Publication Year: 2002 , Page(s): 33 - 37
    Cited by:  Papers (45)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (867 KB) |  | HTML iconHTML  

    The MIT approach to 3D VLSI integration is based on low-temperature Cu-Cu wafer bonding. Device wafers are bonded in a face-to-back manner, with short vertical vias and Cu-Cu pads as the inter-wafer throughway. In our scheme, there are several reliability criteria, which include: (a) structural integrity of the Cu-Cu bond; (b) Cu-Cu contact electrical characteristics; and (c) process flow efficiency and repeatability. In addition, CAD tools are needed to aid in design and layout of 3DICs. This paper discusses recent results in all these areas. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Future SoC design challenges and solutions

    Publication Year: 2002 , Page(s): 534 - 537
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1035 KB) |  | HTML iconHTML  

    SoC (system on a chip) design creates tremendous design challenges to the traditional VLSI ASIC design. It covers not only the traditional DSM (deep sub-micron) issues but also the integration issues such as IP and signal integrity especially for integrated digital/analog system such as Bluetooth. Besides. power consumption and power delivery also impose huge design constraints to the already difficult situation especially for the portable and mobile devices. This talk will introduce and analysis the potential SoC issues and potential solutions from the architecture level to the circuit level. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.