Proceedings International Symposium on Quality Electronic Design

21-21 March 2002

Filter Results

Displaying Results 1 - 25 of 87
  • Proceedings International Symposium on Quality Electronic Design

    Publication Year: 2002
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (401 KB)

    The following topics are dealt with: interconnect extraction and modeling; design for process variations; design issues for power and noise management; low power design techniques; quality and interoperability of EDA tools; power, signal and EMI analysis and optimization; verification in achieving design quality; advanced device technology issues in circuit design; design for test; methods and met... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Productivity optimization techniques for the proactive semiconductor manufacturer

    Publication Year: 2002
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (174 KB)

    Summary form only given. The experienced semiconductor manufacturer is often confronted by apparently similar products that yield drastically different productivities. The same processes are used to fabricate these chips, yet the manufacturer's costs are clearly different. The customers expect similar pricing and a deviation must be accompanied by a credible explanation. Design for manufacturabili... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Wireless systems-on-a-chip design

    Publication Year: 2002
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (304 KB)

    Summary form only given. There is a fundamental shift that is occurring in the implementation of wireless systems. Not only is the underlying technology shifting to mainstream CMOS technology, but the applications and specifications of the supported links are also rapidly evolving. The multiple inter-related technologies required for implementation of such wireless systems requires a co-design str... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Tomorrows high-quality SoCs require high-quality embedded memories today

    Publication Year: 2002
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (223 KB)

    Summary form only given. Embedded memories increasingly dominate SoC designs - whether chip area, performance, power consumption, manufacturing yield or design time are considered. ITRS data indicate that the embedded memory contents of ICs may increase from 20% in 1999 to 90% at the 50 nm node by the end of the decade. Therefore, even more than at present, the success of future SoC design will de... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient closed-form crosstalk delay metrics

    Publication Year: 2002, Page(s):431 - 436
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (249 KB) | HTML iconHTML

    In this paper we present efficient closed-form formulas to estimate capacitive coupling-induced delay in distributed RC coupling network. The efficiency of our approach stems from the fact that only five basic operations are used in the expressions: addition, subtraction, multiplication, division, and square root. The formulas do not require exponent computation or numerical iterations. Our estima... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Author index

    Publication Year: 2002, Page(s):539 - 541
    Request permission for commercial reuse | |PDF file iconPDF (250 KB)
    Freely Available from IEEE
  • Statistical methods for the determination of process corners

    Publication Year: 2002, Page(s):133 - 137
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (304 KB) | HTML iconHTML

    Presents a statistical method to determine the variation of the production process of MOS transistors by finding the wafers that have parameter values on the boundary of the distribution. For the selection of the wafers a location depth method is used. Since it would be too time-consuming to determine the SPICE parameters for all the wafers and compute the boundary wafers in the SPICE domain, we u... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Impact analysis of process variability on clock skew

    Publication Year: 2002, Page(s):129 - 132
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (259 KB) | HTML iconHTML

    This paper presents a methodology for the statistical analysis of clock tree structures. It allows to accurately predict and analyze the impact of process variation on clock skew. The methodology is divided in three phases. The first phase is a topological analysis used to screen non-critical network configurations, which does not require computationally expensive steps such as parasitic extractio... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Automatic test program generation from RT-level microprocessor descriptions

    Publication Year: 2002, Page(s):120 - 125
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (405 KB) | HTML iconHTML

    The paper addresses the issue of microprocessor and microcontroller testing, and follows an approach based on the generation of a test program. The proposed method relies on two phases: in the first, a library of code fragments (named macros) is generated by hand based on the knowledge of the instruction set, only. In the second phase, an optimization algorithm is run to suitably select macros and... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Testing of analogue circuits via (standard) digital gates

    Publication Year: 2002, Page(s):112 - 119
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (540 KB) | HTML iconHTML

    The possibility of using window comparators for on-chip (and potentially on-line) response evaluation of analogue circuits is investigated. No additional analogue test inputs are required and the additional circuitry can be realised either by means of standard digital gates taken from an available library or by full custom designed gates to obtain an observation window tailored to the application.... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of reconfigurable access wrappers for embedded core based SOC test

    Publication Year: 2002, Page(s):106 - 111
    Cited by:  Papers (7)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (308 KB) | HTML iconHTML

    Testing of embedded core based system-on-chip (SOC) ICs is a well known problem, and the upcoming IEEE P1500 (SECT) standard proposes DfT solutions to alleviate it. One of the proposals is to provide every core in the SOC with test access wrappers. Previous approaches to the problem of wrapper design have proposed static core wrappers, which are designed for a particular test access mechanism (TAM... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Extending the viability of IDDQ testing in the deep submicron era

    Publication Year: 2002, Page(s):100 - 105
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (298 KB) | HTML iconHTML

    IDDQ testing has become a widely accepted defect detection technique in CMOS ICs. However, its effectiveness in deep submicron is threatened by the increased transistor sub-threshold leakage current. In this paper, a new IDDQ testing scheme is proposed. This scheme is based on the elimination, during IDDQ testing, of the normal leakage current from the sensing node... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Inductance aware interconnect scaling

    Publication Year: 2002, Page(s):43 - 47
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (266 KB) | HTML iconHTML

    This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance effects do not start dominating the overall interconnect performance. It is shown that for unscaled global lines, inductance effects increase as technology scales while for the scaling scheme proposed by ITRS (1999), interconnects become extremely resistive and, while inductance effects diminish with ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Coupled electromagnetic-circuit simulation of arbitrarily-shaped conducting structures using triangular meshes

    Publication Year: 2002, Page(s):38 - 42
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (295 KB) | HTML iconHTML

    The partial-element-equivalent-circuit (PEEC) approach is an effective method to convert three-dimensional on-chip multiconductor structures to circuit-level descriptions. In this paper, a triangular-mesh-based PEEC approach is described, wherein the surfaces of arbitrarily-shaped conducting structures are represented by triangular mesh tesselations. A coupled EM-circuit formulation is obtained th... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Test generation and fault modeling for stress testing

    Publication Year: 2002, Page(s):95 - 99
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (245 KB) | HTML iconHTML

    Voltage stress testing has long been used as a reliability screen. Significant effort has been devoted in the reliability physics literature to setting of stress voltages. Chang and McCluskey formalized the test aspects of voltage stressing in their works on "SHOVE (SHort VOltage Elevation)" testing. Their work deals with 3.3V and 5V technologies where Fowler-Nordheim tunneling is dominant and sug... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fabrication technologies for three-dimensional integrated circuits

    Publication Year: 2002, Page(s):33 - 37
    Cited by:  Papers (58)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (867 KB) | HTML iconHTML

    The MIT approach to 3D VLSI integration is based on low-temperature Cu-Cu wafer bonding. Device wafers are bonded in a face-to-back manner, with short vertical vias and Cu-Cu pads as the inter-wafer throughway. In our scheme, there are several reliability criteria, which include: (a) structural integrity of the Cu-Cu bond; (b) Cu-Cu contact electrical characteristics; and (c) process flow efficien... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Interoperability and quality of new EDA tools for sequential logic synthesis

    Publication Year: 2002, Page(s):87 - 92
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (263 KB) | HTML iconHTML

    One of the main problems in design of modem microelectronic systems is achieving consistent high quality results along the entire EDA tool chain. Using the sequential logic synthesis tools for a case study, this paper shows how important is the consistent tool collaboration for the quality of the final result. In the paper, a new uniform and consistent information-driven logic synthesis approach i... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Formulae for performance optimization and their applications to interconnect-driven floorplanning

    Publication Year: 2002, Page(s):523 - 528
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1723 KB) | HTML iconHTML

    As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are the most effective and popular techniques to reduce interconnect delay and are traditionally applied to post-layout, optimization. As the SIA technology roadmap predicts, however, the number of interconnections among diff... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Advancing quality of EDA software

    Publication Year: 2002, Page(s):81 - 86
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (276 KB) | HTML iconHTML

    In the fast-paced electronics market, design engineers face incredible challenges to keep up with increasing technology complexity and time-to market pressures. Under these challenges, design engineers have been saying that quality issues with their EDA software tools cost them dearly in lost productivity and in missing tight deadlines. Therefore, improving the quality of EDA software tools and pr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A thermal-aware superscalar microprocessor

    Publication Year: 2002, Page(s):517 - 522
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (248 KB) | HTML iconHTML

    A thermal-aware technique is proposed to minimize the performance impact when thermal/power control mechanism is triggered. This technique, called thermal-aware microprocessor (TAM), uses on-chip thermal sensors to detect hot-spots within the microprocessor die. There is a secondary pipeline within the core. It is architecturally simple with ultra low power implementation. This secondary pipeline ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A qualification platform for design reuse

    Publication Year: 2002, Page(s):75 - 80
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (3259 KB) | HTML iconHTML

    The application and development of reusable components (intellectual property, IP) has become a regular part of modern design practices. The IP provider on one side and the IP integrator (user) on the other may be in the same company or separate participants in the microelectronic design market. In both cases, the transfer of IP remains a complex and time-consuming task. The qualification of IP ga... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Device physics impact on low leakage, high speed DSP design techniques

    Publication Year: 2002, Page(s):349 - 354
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (372 KB) | HTML iconHTML

    The limitations of implementing low leakage schemes and their application to current state of the art components is discussed In addition to source subthreshold leakage, both gate induced diode leakage current and tunneling gate leakage current must be comprehended A viable leakage reduction strategy requires extensive modeling of circuits in the standby mode as well as new demands on the understa... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Noise injection and propagation in high performance designs

    Publication Year: 2002, Page(s):425 - 430
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (246 KB) | HTML iconHTML

    Signal integrity has become a critical issue in the design of high-performance circuits. Noise on a net arises both through propagation of noise from previous stages through the driver gate of the net and through injection of new noise through coupling capacitance with neighboring nets. Typically, propagated noise and injected noise are added linearly to simplify the analysis and increase its effi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Trends in low power digital system-on-chip designs

    Publication Year: 2002, Page(s):373 - 378
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (261 KB) | HTML iconHTML

    A study of the future trends in low-power System-on-Chip (SoC) designs is presented, based on the recently announced ITRS-2001 technology characteristics for both high-performance and low-power devices from 2001 to 2016. We forecast the logic/memory composition of a reference low-power PDA design with an area constraint of 1 cm2 using both a bottom-up, power dissipation-constrained chip... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Does Q = MC2? (On the relationship between Quality in electronic design and the Model of Colloidal Computing)

    Publication Year: 2002, Page(s):451 - 457
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (428 KB) | HTML iconHTML

    This paper introduces colloidal computing as an alternative to the classical view on computing systems in terms of design feasibility, application adaptability and better energy-performance trade-offs. In colloidal computing, simple per computational particles are dispersed into a communication medium which is inexpensive, (perhaps) unreliable, yet sufficiently fast. This type of clustering into c... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.