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Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design

2002

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  • A new divide and conquer method for achieving high speed division in hardware

    Publication Year: 2002, Page(s):535 - 540
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (298 KB) | HTML iconHTML

    Presents a new method of performing division in hardware and explores different ways of implementing it. This method involves computing a preliminary estimate of the quotient by splitting the dividend, performing division of each of the parts in parallel and merging them. The estimate is refined iteratively to get the final quotient. This method is significantly fast since it carries out parallel ... View full abstract»

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  • Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design

    Publication Year: 2002
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (446 KB)

    The following topics are dealt with: low power; interconnects; synthesis; analogue design; verification; VLSI architecture; testing; embedded systems; and layout. View full abstract»

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  • Consumer digitization: accelerating DSP applications, growing VLSI design challenges

    Publication Year: 2002, Page(s):3 - 4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (189 KB) | HTML iconHTML

    Summary form only given. Two new technologies have emerged to lead the Internet Age: Digital Signal Processors (DSPs) and analog semiconductors. One of the key challenges of the dramatic growth and widespread application of DSPs is in terms of the increasing complexities of VLSI design. The challenge of integrating more transistors, but using less power, has led to a dramatic evolution of semicond... View full abstract»

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  • LSI design in the 21/sup st/ century: key changes in sub-1V giga-integration era

    Publication Year: 2002
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    Summary form only given. Conventional CMOS technology will face difficulties in the sub-0.1 /spl mu/m, sub-1 V region. Random-modulation CMOS, which assigns multiple threshold levels in the same block through the use of sophisticated CAD tools, will emerge as a key technology in this new regime. Beginning with this first step, the era of "complex CMOS", which requires complicated design elaboratio... View full abstract»

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  • Electronic industry on fire: how to survive and thrive [integrated circuit design]

    Publication Year: 2002
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (255 KB)

    Summary form only given. With changes in technology, end markets, and financial markets, the electronics industry has experienced a dramatic downturn over the last year. Many companies will not survive. Those that do will focus on their core competencies, not tangential skills that may not be their area of strength. Successful electronics companies will also take steps to reduce uncertainty in the... View full abstract»

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  • Digital watermarking

    Publication Year: 2002, Page(s):7 - 8
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (187 KB)

    Summary form only given. The ability to represent audio and video digitally and its vast popularity poses enormous challenges in protection against unauthorized use, copy and distribution in open, highly uncontrolled Internet environment. Digital watermarking, a technology for insertion of imperceptible information into multimedia content offers a solution for authentication and suitable action th... View full abstract»

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  • Functional verification of system on chips - practices, issues and challenges

    Publication Year: 2002, Page(s):11 - 13
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (191 KB) | HTML iconHTML

    Summary form only given. In a complex SoC design flow functional verification is very important; any behavioral or functional bug escaping this phase will not be detected in the subsequent implementation phases and will surface only after the first silicon is integrated into the target system, resulting in costly design and silicon iterations. A number of academic and industrial research laborator... View full abstract»

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  • System-level design of embedded media systems

    Publication Year: 2002, Page(s):14 - 15
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    Summary form only given. Reports on system-level design practices in Philips. First we present the design problems encountered in the development of embedded media systems for the consumer market. The characteristics and requirements of the consumer electronics domain are presented. We focus on high performance video applications and the demands that these applications put on architectures of embe... View full abstract»

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  • Trends and challenges in VLSI technology scaling towards 100 nm

    Publication Year: 2002, Page(s):16 - 17
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm generation and beyond. The first focus area is the process technology, including transistor scaling... View full abstract»

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  • Mathematical methods in VLSI

    Publication Year: 2002, Page(s):18 - 19
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (185 KB) | HTML iconHTML

    Summary form only given. The theme of the tutorial is the use of mathematical methods in VLSI. The traditional use of mathematics in engineering disciplines is via mathematical modeling - concepts and interactions in the problem domain are mapped to objects and relationships of a specific mathematical topic and then the formal deductions within the topic are re-interpreted in the problem domain. A... View full abstract»

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  • Electronic testing for SOC designers

    Publication Year: 2002
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (178 KB)

    Summary form only given. The presentation is divided into three parts. Part I contains definition of test and its motivation, test process and automatic test equipment (ATE), test economics and product quality, and fault modeling. Part II includes logic and fault simulation, testability measures, combinational and sequential ATPG, memory test, DSP-based analog test, model-based analog test, delay ... View full abstract»

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  • Specification, modeling and design tools for system-on-chip

    Publication Year: 2002, Page(s):21 - 23
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (190 KB) | HTML iconHTML

    Summary form only given. Illustrates first the languages and models of computation available to the system-level. designer to capture precisely and unambiguously requirements. We discuss for what application domain and platform each language is most appropriate, focusing mostly on platform-independent languages and MOCs, since they support the greatest freedom in mapping choice. We will then discu... View full abstract»

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  • MEMS: technology, design, CAD and applications

    Publication Year: 2002, Page(s):24 - 25
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    Summary form only given. Micromachined electro-mechanical systems(MEMS), also called microfabricated systems (MS), have evoked great interest in the scientific and engineering communities. This is primarily due to several advantages that MEMS offer: orders of magnitude smaller size, better performance than other solutions, possibilities for batch fabrication and cost-effective integration with ele... View full abstract»

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  • Logic design of asynchronous circuits

    Publication Year: 2002, Page(s):26 - 27
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (185 KB) | HTML iconHTML

    Summary form only given. This tutorial aims at motivating the audience to consider asynchronous circuits as a competitive alternative to solve some of the design problems inherent to submicron technologies. One of the main reasons why designers are reluctant to incorporate asynchrony in their systems is the difficulty to design asynchronous circuits. Asynchronous circuits are promising to tackle p... View full abstract»

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  • Tutorial on modeling parasitic coupling effects in reliability verification

    Publication Year: 2002
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (170 KB)

    Summary form only given. As technology scaling continues in the deep sub-micron domain, interconnect parasitics have become dominant in determining chip performance and functionality. R(L)C parasitics play a major role in chip performance, functionality and signal integrity. In addition, parasitics have significant impact on chip reliability due to electromigration (EM), timing dependent dielectri... View full abstract»

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  • Definition, design & development of the IXE2424 Network Switch/Router ASIC

    Publication Year: 2002
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB)

    Summary form only given. This paper highlights key aspects of the cumulative technical experience of the past two years at Intel, Bangalore, in defining, designing, implementing and ramping to production of the Intel IXE2424 ASIC. The IXE2424 is a Layer 2-3-4 Network Switch/Router, consisting of over twenty-five million transistors, manufactured in 0.18 u 1P6M CMOS process. The team at Bangalore c... View full abstract»

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  • Author index

    Publication Year: 2002, Page(s):806 - 809
    Request permission for commercial reuse | PDF file iconPDF (203 KB)
    Freely Available from IEEE
  • On routing demand and congestion estimation for FPGAs

    Publication Year: 2002, Page(s):639 - 646
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB) | HTML iconHTML

    Interconnection planning is becoming an important design issue for ASICs and large FPGAs. As the technology shrinks and the design density increases, proper planning of routing resources becomes all the more important to ensure rapid and feasible design convergence. One of the most important issues for planning interconnection is the ability to predict the routability of a given placed design. Thi... View full abstract»

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  • Probabilistic analysis of rectilinear Steiner trees

    Publication Year: 2002, Page(s):484 - 488
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (518 KB) | HTML iconHTML

    The Steiner tree is a fundamental concept in automatic interconnect optimization for VLSI design. We present a probabilistic analysis method for constructing rectilinear Steiner trees. The best solution in a statistical sense is obtained for any given set of N points. Experiments show that our results are better than those by previous techniques and are very close to the optima View full abstract»

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  • A new synthesis of symmetric functions

    Publication Year: 2002, Page(s):160 - 165
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (278 KB) | HTML iconHTML

    A new approach to synthesizing totally symmetric Boolean functions is presented. First, a novel cellular array is introduced for synthesizing unate symmetric functions. Using this module, a general symmetric function is then realized following a unate decomposition method. The cellular structure is simple and universal - it uses only 2-input, 2-output AND-OR cells, and admits a recursive construct... View full abstract»

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  • Impact of technology scaling on metastability performance of CMOS synchronizing latches

    Publication Year: 2002, Page(s):317 - 322
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (245 KB) | HTML iconHTML

    In this paper, we use circuit simulations to characterize the effects of technology scaling on the metastability parameters of CMOS latches used as synchronizers. We perform this characterization by obtaining a synchronization error probability curve from a histogram of the latch delay. The main metastability parameters of CMOS latches are τm and Tw. τm is ... View full abstract»

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  • Efficient macromodeling for on-chip interconnects

    Publication Year: 2002, Page(s):561 - 566
    Cited by:  Papers (3)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1008 KB) | HTML iconHTML

    The improved T and improved Π models are proposed for on-chip interconnect macromodeling. Using global approximations, simple approximation frames are derived and applied to modeling of on-chip distributed RC interconnects. The applications lead to equivalent circuit models for on-chip interconnects, which are represented by the improved T and improved Π models. By matching the first three m... View full abstract»

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  • Strategies for improving data locality in embedded applications

    Publication Year: 2002, Page(s):631 - 636
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (442 KB) | HTML iconHTML

    This paper introduces a dynamic layout optimization strategy to minimize the number of cycles spent in memory accesses in a cache-based memory environment. In this approach, a given multi-dimensional array may have different memory layouts in different segments of the same application if doing so improves data locality (cache behavior) beyond the static approaches that fix memory layouts at specif... View full abstract»

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  • Simultaneous circuit transformation and routing

    Publication Year: 2002, Page(s):479 - 483
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (242 KB) | HTML iconHTML

    In this paper, we propose a new methodology to integrate circuit transformation into routing. More specifically, this paper shows an approach for performing routing and wire reconnection simultaneously. To accomplish this, we introduce a new logic representation that implements all possible wire reconnections implicitly by enhancing global flow optimization techniques. Since our method takes into ... View full abstract»

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  • Prioritized prime implicant patterns puzzle for novel logic synthesis and optimization

    Publication Year: 2002, Page(s):155 - 159
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (309 KB) | HTML iconHTML

    Comparing CMOS logic with pass-transistor logic, a question was raised in the minds of the authors: "does any rule exist that contains all good?" This paper reveals novel logic synthesis and optimization procedures for full swing arbitrary logic function. The novel procedures are called prioritized prime implicant patterns puzzle (PPIPP). Following the proposed procedures, we can get a new hybrid ... View full abstract»

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