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Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on

Date 14-17 Aug. 2001

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  • Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)

    Publication Year: 2001
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  • Simple criteria to evaluate a converter as an active power factor corrector

    Publication Year: 2001 , Page(s): 989 - 992 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (258 KB) |  | HTML iconHTML  

    Limited dynamics of power stages in active power factor correction circuits sets a bound on a degree to which current can be shaped. In this paper, a general approach to evaluate the converter dynamics versus the necessary dynamics for operation as an APFC is introduced. A simple criterion is developed in the time domain that enables characterization of converter topology and component values. Calculations are validated by simulation and experimental results for a boost converter as an example. View full abstract»

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  • Author index

    Publication Year: 2001 , Page(s): 997 - 1000
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    Freely Available from IEEE
  • Reference to output frequency compensation of bidirectional DC-DC converter

    Publication Year: 2001 , Page(s): 993 - 996 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (190 KB) |  | HTML iconHTML  

    A bidirectional flyback converter with output voltage tracking capabilities was designed and tested. For the first time an H∞ approach was used for a controller design. A better performance of the H∞ controller over a traditional reference-to-output frequency-compensated one was shown. Theoretical results were validated by simulations and experiments View full abstract»

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  • A novel absolute value representation of continuous piecewise linear functions

    Publication Year: 2001 , Page(s): 870 - 873 vol.2
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    This paper gives a novel generalized absolute value representation of two-dimensional continuous piecewise-linear (PWL) functions, which is obtained by analyzing the fundamental structures of a PWL function instead of its subdomains. The availability of the novel representation is proven View full abstract»

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  • Effects of active microwave device parameters on microwave harmonic frequency generators

    Publication Year: 2001 , Page(s): 777 - 780 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (142 KB) |  | HTML iconHTML  

    Modern microwave and RF systems are increasingly utilizing internal frequency upconversion techniques. This paper develops improved methods of designing active microwave frequency multipliers utilizing MESFET and HEMT devices. The methods extend and improve the accuracy of classical techniques developed over the past few years View full abstract»

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  • Hybrid dynamic neural learning (HDNL) in control applications

    Publication Year: 2001 , Page(s): 627 - 635 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (338 KB) |  | HTML iconHTML  

    Presents a new, simple, and versatile neural network controller paradigm, which applies a hybrid learning approach. The major advantage of this controller is that the network learning process is faster. The controller first applies a nonlinear neuron computation scheme to make functional association of input signals to an internal representation in frequency domain. It then maps the internal representation to desired patterns as the output of the controller. Unsupervised learning is conducted for tuning the synaptic weights from the input layer to the internal layer. Supervised learning is employed to tune the synaptic weights for output pattern matching. The hybrid neural controller is especially capable of handling highly noise-corrupted signals in many real-world control applications, such as real-time robot motion planning and control. The hybrid neural network controller was applied to a nonlinear process involving controlling the position of a bouncing ball over a rough moving surface. This system is a typical example of an uncertain model subjected to various types of noises. The simulation was done in a MATLAB environment View full abstract»

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  • Single-resistance-controlled sinusoidal oscillators employing single FTFN and grounded capacitors

    Publication Year: 2001 , Page(s): 874 - 877 vol.2
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (125 KB) |  | HTML iconHTML  

    In this study new single-resistance controlled sinusoidal oscillator topologies are proposed. All of the proposed oscillators use single FTFN, two grounded capacitors which is suitable for IC implementation, and five resistors. They have passive sensitivities less than unity. The oscillators provide non-interactive control of oscillation condition and oscillation frequency and they can easily be converted to voltage-controlled oscillators. Theoretical analyses are verified with PSPICE simulations View full abstract»

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  • An investigation into the use of a keypad-isomorphic symbolism as a method to increase the speed of human-computer interaction

    Publication Year: 2001 , Page(s): 512 - 515 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (239 KB) |  | HTML iconHTML  

    This paper introduces a new human-computer interface concept based on the use of keypad-isomorphic symbols. These symbols form the basis of a methodology, referred to as "binagraphics," that is designed to significantly reduce the time required for humans to enter discrete commands to the computer. Additionally, this symbol-based methodology enables a particular one-handed six-degree-of-freedom (6DOF) control device to be used for object and viewpoint manipulations in virtual 3-dimensional space. In total, the symbols of the methodology can be thought of as the isomorphisms of all keyswitch combinational input possibilities of the standardized telephone numeric keypad. The symbols, as well as the keypad combinations, are combinations of binary elements. The binary symbols of the methodology will be called "binagrams" for convenience, and they are displayed on the computer display to provide a one-to-one mapping between human control space and computer display space. The keypad of the control device is not used in the conventional manner; rather, it is positioned upright and operated from reverse View full abstract»

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  • Implementation, verification and synthesis of the Gigabit Ethernet 1000BASE-T physical coding sublayer

    Publication Year: 2001 , Page(s): 556 - 559 vol.2
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (205 KB) |  | HTML iconHTML  

    IEEE standard 802.3ab 1000BASE-T (Gigabit Ethernet) physical layer standard offers a cost-effective solution that upgrades the existing networks to 1000 Mbps data rates. It provides 1 Gbps Ethernet signal transmission over four pairs of category 5 unshielded twisted pair (UTP) cable using the 5-level coding scheme. The Physical Coding Sublayer (PCS) of this standard was simulated using Verilog HDL and synthesized using Synopsys. Two synthesis techniques, hierarchical optimization and hierarchical-flattening optimization, were chosen to compare the tradeoffs between them. The automation of the synthesis was accomplished with the synthesis script files View full abstract»

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  • Versatile current-mode loser-take-all circuits for analog decoders

    Publication Year: 2001 , Page(s): 748 - 751 vol.2
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    A new concept for finding the minimum between two variables is described in this paper. Two types of hardware implementation of the novel concept are presented in CMOS. The ease of adding and/or subtracting currents as compared to voltage summation is fully utilized to realize versatile current-mode minimum seeking circuits that could find application in analog decoders. The approach presented also has the potential of being extended in a highly modular architecture to find the minimum of an array of inputs in current-mode. The overall circuitry uses single and double output current mirrors as internal processing units connected between a 3.3 V power supply and could resolve a current difference of at least 1.5 μA View full abstract»

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  • An FSK demodulator for Bluetooth applications having no external components

    Publication Year: 2001 , Page(s): 915 - 918 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (202 KB) |  | HTML iconHTML  

    An injection-locked oscillator in combination with a phase detector is shown to make a very effective FSK demodulator for Bluetooth applications. The dynamic behavior allows automatic tuning from outside the locking range. Two tuning methods are described which eliminate the need for external components. A cancellation technique is used which minimizes filtering requirements. The demodulator was fabricated in a 0.4 μm BiCMOS technology View full abstract»

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  • Optimal-weights sensors-measurement fusion using genetic algorithms

    Publication Year: 2001 , Page(s): 537 - 542 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (298 KB) |  | HTML iconHTML  

    Although there are many simulated Genetic Algorithms (GAs) in applications, less research has been directed toward their practical hardware implementations. In this paper we present a GA for optimum sensors-measurement fusion and characteristic weights. A multilevel verification of the GA is performed via the Mentor Graphics Design Architect (DA) and ModelSim CAD tools. In particular the design of efficient universal multipliers, dividers, and their integrated circuits is addressed. Effective mutation and crossover approach has been implemented in the GA system operation. It requires 960 clock cycles for complete iteration of 64 chromosomes, each with 3 genes of two binary-bits. This requires only 12 μsec when implemented in the 0.25 μm CMOS technology. The GA system is developed for a preprocessing unit to select optimal weights from real-time sensors measurement, and for fused measurements as in an electronic nose, integrated accelerometer systems, and for performance enhancement of recurrent dynamic neural networks in noisy environments. The proposed approach, simulation results, and possible experimental results are presented View full abstract»

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  • A coupled two-stage ring oscillator

    Publication Year: 2001 , Page(s): 878 - 881 vol.2
    Cited by:  Papers (10)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (206 KB) |  | HTML iconHTML  

    Modeling, analysis and test results of a fabricated coupled two-stage ring oscillator are presented in this paper. The oscillator consists of two two-stage ring oscillators which are coupled to each other and oscillate with the same frequency, but with 45 degrees phase difference resulting in two sets of quadrature outputs. It has been proven analytically that the coupled ring oscillator has an inherent capability of oscillating with frequencies as high as 1.96 times that of a single three-stage ring. A coupled two-stage ring oscillator, fabricated in CMOS 0.18 μm technology, is described. This VCO has frequency tuning range of 2.5 - 9 GHz for a 1.8 V power supply voltage View full abstract»

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  • Exploiting bondwire parasitic impedance in the design of a 1.6 GHz narrow-band CMOS low noise amplifier

    Publication Year: 2001 , Page(s): 804 - 807 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (195 KB) |  | HTML iconHTML  

    This paper presents a new technique for efficiently utilizing the parasitic impedance of bondwires in the design of a 1.6 GHz high performance narrow-band Low Noise Amplifier (LNA). Bondwires have reasonably predictable parasitic impedance and have much higher quality factors compared to on-chip spiral inductors. The proposed LNA design uses bondwires to provide the needed inductive reactance and does not use any on-chip spiral inductors. Series capacitors are used to control the inductive reactance of bondwires. HSPICE simulations show that the LNA achieves a noise figure NF of only 2.0 dB in 0.6 μm CMOS process technology. It has S11 of -10.04 dB, S22 of -29.3 dB, S21 of 21.2 dB, input referred IP3 of -8 dBm, and consumes 14.94 mW from a 2.5 V power supply View full abstract»

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  • An interleaved low-voltage half-bridge converter with master-slave peak current control

    Publication Year: 2001 , Page(s): 957 - 959 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (178 KB) |  | HTML iconHTML  

    An interleaved low-voltage half-bridge converter is proposed in this paper. With a master-slave peak current control, charge balances of the main transformers are automatically achieved. Thus current runaway is avoided without an additional correction circuit. It is shown that the steady state analysis and simulation results are in good agreement. A 48 V input, 1.5 V/60 A output prototype is built to verify the proposed control method View full abstract»

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  • Improved modeling for transit time and excess phase delay of advanced bipolar transistors at high current densities

    Publication Year: 2001 , Page(s): 844 - 847 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (159 KB) |  | HTML iconHTML  

    Bias-dependent data of the forward transit time and excess phase delay at high current densities are extracted using an accurate measurement technique based on Z-parameter equations. Using these data, simple expressions of these parameters have been developed to improve a RF large-signal bipolar transistor model, and their accuracy is verified by showing good agreements with measured data View full abstract»

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  • A high-frequency single-side PWM multiple bus distributed power system

    Publication Year: 2001 , Page(s): 976 - 979 vol.2
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (207 KB) |  | HTML iconHTML  

    The design consideration and implementation of a high frequency (HF) PWM-wave bus distributed power system (DPS) is presented. The system utilizes a 100 kHz, 48 V peak PWM bus for AC voltage distribution. The load converter consists of different level output magamps post-regulators. Bus regulation is accomplished through a simplified front-end design consisting of a boost PFC converter cascaded with a two-switch forward converter. Experimental results are presented for operation at 5 V DC and 3.3 V DC with 200 W output View full abstract»

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  • A wireless MEMS application with dynamic data and strap support system

    Publication Year: 2001 , Page(s): 718 - 721 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (435 KB) |  | HTML iconHTML  

    A wireless MEMS force/pressure/temperature sensor was utilized in the collection of data from a study involving a strap support system to be used in conjunction with human subjects. Both static and dynamic data were collected to demonstrate the efficacy of the sensor described herein. The wireless property and ability to place the sensor at arbitrary points provides great utility for the application of such a MEMS apparatus View full abstract»

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  • A new text-independent method for phoneme segmentation

    Publication Year: 2001 , Page(s): 516 - 519 vol.2
    Cited by:  Papers (16)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (207 KB) |  | HTML iconHTML  

    A new approach for text-independent speech segmentation is proposed. The novelty consists in a preprocessing based on critical-band perceptual analysis and an original algorithm for the individuation of phoneme boundaries. The results are promising since the method gives ~74% of correct segmentation without presenting over-segmentation View full abstract»

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  • Impact of current sensing resistor on required MOSFET aspect ratio in PWM converters

    Publication Year: 2001 , Page(s): 964 - 967 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (127 KB) |  | HTML iconHTML  

    This paper examines the impact of a current sensing resistor used in current-mode control of PWM converters on MOSFET aspect ratio. The results can also be applied to the impact of source parasitic resistance in a power MOSFET. These resistances introduce significant error in the required aspect ratio to achieve a desired maximum current capability. Experimental results are presented showing the validity of the theoretical results View full abstract»

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  • VLSI architecture of QMF for DWT integrated system

    Publication Year: 2001 , Page(s): 560 - 563 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB) |  | HTML iconHTML  

    Wavelet transform has become a suitable tool for DSP signal manipulation especially in image compression. A VLSI implementation of a CMOS circuit realizing a Discrete Wave Transform ( DWT) for Daubecchie's 6 using a novel realization of Quadrature Mirror Filter [QMF] is presented. The new design of the DWT system which is based on a new Finite Impulse Response filter FIR requires less Si area to be implemented, since the FIR filter is implemented using mixed parallel / sequential architecture resulting in reducing the number of binary multipliers used which are the major bottle neck governing the performance of the DSP processing. Consequently, it results in a much faster system. Moreover, the use of parallel multipliers results in less power dissipation View full abstract»

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  • A VHDL software model for networking smart transducers through Bluetooth technology

    Publication Year: 2001 , Page(s): 919 - 922 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (262 KB) |  | HTML iconHTML  

    The interfacing of smart transducers to a wireless medium is an attractive solution for reconfigurable networks but this has not been explored extensively for small-span networks using existing wireless technology. This paper describes a software model for a network infrastructure that enables smart transducer communication through Bluetooth. The design of the network infrastructure is according to the recently standardized IEEE 1451.1 specification and uses the OBEX Session protocol. A proof-of-concept VHDL implementation of the design and the accompanying simulation output are presented View full abstract»

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  • An RF CMOS cascode LNA with current reuse and inductive source degeneration

    Publication Year: 2001 , Page(s): 824 - 828 vol.2
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (186 KB) |  | HTML iconHTML  

    An RF CMOS Low-Noise Amplifier (LNA) is proposed using a current reuse technique (CRT) to increase the amplifier transconductance without increasing power dissipation. The circuit was simulated and designed with 0.5 μm CMOS MOSIS process. At 1 GHz, the LNA noise figure (NF) is 2.7 dB, forward gain is 21.6 dB and reverse isolation is -42.5 dB. The LNA consumes 20.3 mW from a 2.2 V power supply View full abstract»

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  • A new test structure for short and long distance mismatch characterization of submicron MOS transistors

    Publication Year: 2001 , Page(s): 656 - 660 vol.2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (334 KB) |  | HTML iconHTML  

    A new test structure for the characterization of statistical variations of the parameters of submicron MOS devices is presented in this work. The structure has been designed for the estimation of mismatch parameters as a function of the device dimensions and positions in the die. Low area consumption and a reduced measurement time required for the complete mismatch characterization are the main objective of the design. The test structure consisting of about 6000 MOSFETs has been used for mismatch characterization of a 0.18 μm CMOS technology View full abstract»

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