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ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549)

23-25 Oct. 2001

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  • ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549)

    Publication Year: 2001
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    Freely Available from IEEE
  • Authors index

    Publication Year: 2001, Page(s):889 - 893
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    Freely Available from IEEE
  • Optimizing the design for microdisplay on silicon, creating IP modules for a new type of SOC

    Publication Year: 2001, Page(s):785 - 788
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (401 KB) | HTML iconHTML

    A microdisplay chip on silicon is a piece of multi-function and multi-structure SOC (system on chip). From the common circuit of the microdisplay chip, we are able to form several independent IP modules. Then we design a suite of 0.8 μm CMOS basic libraries and IP modules for a microdisplay on silicon with CADENSE. Additionally, we demonstrate the flexible design of a capacitor for the microdis... View full abstract»

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  • A platform for system-on-a-chip design prototyping

    Publication Year: 2001, Page(s):781 - 784
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    System prototyping is an important step in embedded system design, it can be used to validate the system functionality, performance and real time response to environment. A platform containing a microcomputer and a prototyping board is built for system-on-a-chip prototyping. A simple system-on-a-chip prototype reacting with its environment is built demonstrating the usage of the platform. The on c... View full abstract»

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  • A debug sub-system for embedded-system co-verification

    Publication Year: 2001, Page(s):777 - 780
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (450 KB) | HTML iconHTML

    With the development of VLSI, embedded system is growing sharply. A new methodology, Co-design, appeared to meet needs of embedded system designing. System designers require good EDA tools, which support Co-design methodology. Debug is an important part of design process, so we improved a debug subsystem to fit Co-design. Different from traditional software debug tools, the new debug system was de... View full abstract»

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  • Parallel behavior-level simulator based on VHDL-AMS [mixed circuit simulation]

    Publication Year: 2001, Page(s):700 - 703
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (325 KB) | HTML iconHTML

    This paper proposes a novel approach that makes use of a software package named parallel virtual machine (PVM), which allows a researcher to use workstations as nodes in a parallel processing environment to perform a large-scale simulation. The parallel scheme is described, and the computational power and cost effectiveness of PVM are demonstrated on the problem of simulating mixed circuits View full abstract»

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  • A scalable test mechanism and its optimization for test access to embedded cores

    Publication Year: 2001, Page(s):773 - 776
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (369 KB) | HTML iconHTML

    In this paper, a test access mechanism named TESTLINE and its test time and power optimization algorithm for SOC test is presented. TESTLINE just needs 5 pins and can provide high-speed parallel test scheme. TESTLINE has a scalable mechanism. Its schematic can be easily configured according to test time and test power. ILP (Integer Linear Programming) is used to find the optimal results. TESTLINE ... View full abstract»

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  • A new usage of SPICE simulation program [bipolar transistor]

    Publication Year: 2001, Page(s):696 - 699
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (301 KB) | HTML iconHTML

    A new usage of SPICE simulation program, for the purpose of verifying the theory of the so-called edge-crowding effect of the emitter current in a bipolar transistor, is put forward. The conclusion is that the use of SPICE is successful, and the simulated distribution of base voltage and density of emitter current is coincident with that given by the theory View full abstract»

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  • Formal verification of embedded SoC

    Publication Year: 2001, Page(s):769 - 772
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (399 KB) | HTML iconHTML

    SoC (System on a Chip) are becoming more and more popular due to their widespread applications and the improved techniques. In many cases, the safety is very important. For SoC, the traditional validation techniques, such as simulation and testing, are not viable. Formal methods are becoming a practical alternative to ensure the correctness of the design. In this paper, we investigate the modeling... View full abstract»

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  • Module recognition and its application to LVS of ASIC

    Publication Year: 2001, Page(s):693 - 695
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB) | HTML iconHTML

    LVS (Layout Versus Schematic) is an important procedure in ASIC design. LVS includes 2 steps: extraction of devices and net-lists from layout with an EDA system to form the schematic, the so-called "extracted schematic", and identification and verification of the extracted schematic with another schematic designed independently upon layout. The former is more important than the latter. Module reco... View full abstract»

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  • The design of a high performance and low power embedded microprocessor core OM80C51

    Publication Year: 2001, Page(s):765 - 768
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (354 KB) | HTML iconHTML

    OM80C51 is an embedded microprocessor core compatible with 80C51. But some of its performances are better than those of 80C51. For instance, it has shorter instruction cycles for most instructions, a more efficient power management system, and a customizable interrupt system and periphery circuits, with an area of about 7500 gates. All of the above make it attractive for embedded system applicatio... View full abstract»

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  • A hierarchical circuit extraction based on scan line

    Publication Year: 2001, Page(s):689 - 692
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (370 KB) | HTML iconHTML

    A method for hierarchical layout circuit extraction is presented. It uses double scan lines method to search for overlapping area between instances and physical layers, analyze the connectivity between the layers to obtain the transistors and the nets. This analysis is done from the bottom up, after obtaining the connectivity, it merges the nets connected through instances and obtains the correct ... View full abstract»

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  • An approach to reducing power consumption during delay test application

    Publication Year: 2001, Page(s):620 - 623
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (413 KB) | HTML iconHTML

    This paper presents an approach to reducing power consumption during delay test application. It is based on a re-ordering of the test-pairs in the test sequences to minimize the switching activity of the circuit-under-test during test application. Hamming distance between test-pairs is used to guide test-pair re-ordering. This guarantees a decrease in power consumption without reducing delay fault... View full abstract»

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  • The design of a 32 bit floating-point RISC microprocessor

    Publication Year: 2001, Page(s):760 - 764
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (455 KB) | HTML iconHTML

    This paper introduces the design of a 32 bits floating-point RISC Microprocessor. The architecture, basic functional units and their implementation are mainly discussed. When it is fabricated in a 1.2-μm two-metal CMOS process, the area is 8.3 mm* 8.3 mm, and the operation frequency can reach 20 Mhz View full abstract»

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  • Integrated floorplanning and power supply planning

    Publication Year: 2001, Page(s):194 - 197
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (449 KB) | HTML iconHTML

    The power supply planning is very important for high performance VLSI design. An algorithm is proposed, which deals with the design and optimization of tree-based power/ground network in the BBL-based VLSIs. The object of the algorithm is to minimize the routing area used by a power tree. This paper presented an integrated floorplanning and power supply planning algorithm for BBL-based VLSI, which... View full abstract»

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  • A compact algorithm for placement design using corner block list representation

    Publication Year: 2001, Page(s):146 - 149
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (650 KB) | HTML iconHTML

    Corner Block List (CBL) was recently proposed as an efficient representation of general packing of rectangles. Although the original method is really innovative, there still remains room of improvement. This paper proposes a compact algorithm for placement based on corner block list. By introducing the dummy blocks in CBL, our algorithm can intellective employ dummy blocks in the packing to repres... View full abstract»

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  • QFP package analysis using partial element equivalent circuits

    Publication Year: 2001, Page(s):685 - 688
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (271 KB) | HTML iconHTML

    The partial element equivalent circuit (PEEC) technique is employed to model the electrical properties of the generic 64-lead quad-flat-pack (QFP). The model for the package includes many details, such as the leads, bonding wires and finite-size dielectrics. This model is used to investigate the parasitic effect of the package. As an example, the equivalent circuit is used to simulate the simultan... View full abstract»

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  • Design of mixed-signal circuit for testability

    Publication Year: 2001, Page(s):616 - 619
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (433 KB) | HTML iconHTML

    The test and design for testability methods for each type of block exist but assume a direct access to the block under test. Thus, an additional design for testability structure using boundary scan and mixed-signal test bus is incorporated for effective test application. With this design, separate specialized tests are applied to analog and digital parts, as well as to interconnects. The area over... View full abstract»

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  • IP reusable design methodology

    Publication Year: 2001, Page(s):756 - 759
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (459 KB) | HTML iconHTML

    The rapid increase in IC design complexity and greater time-to-market pressure require improving design productivity and reducing product cycle time and development cost, therefore it is necessary to reuse complex pre-defined design and blocks develop new SOC design methodology to improve design productivity. In this paper, IP reusable design methodology is studied from module level and system lev... View full abstract»

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  • EVBCS: new equivalence verification algorithm based on OBDD and circuit structure

    Publication Year: 2001, Page(s):190 - 193
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (470 KB) | HTML iconHTML

    In this paper, an algorithm, EVBCS, for formal verification of combinational logic circuits, is proposed. It combines BDD and structure isomorphism techniques. It also uses a heuristic method to select a set of internal signals (cutline) to reduce the size of BDDs to be created. The algorithm is demonstrated on ISCAS'85 benchmarks using synthesis and optimization tools. The experiment results show... View full abstract»

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  • Implementation of MPEG-2 transport stream remultiplexer with CPLD

    Publication Year: 2001, Page(s):390 - 392
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (290 KB) | HTML iconHTML

    Design of transport stream (TS) remultiplexer with CPLD is described in this paper. PID mapping and PCR correction are two important functions of TS remultiplexer. For saving resource, simple RAM architecture is substituted by the combination of content-addressable-memory (CAM) and RAM, when forming a high-speed PID information table. An uncomplex algorithm of PCR correction is given in this paper... View full abstract»

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  • Distinguishing variables of Boolean function via distinct subBDDs

    Publication Year: 2001, Page(s):141 - 145
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (426 KB) | HTML iconHTML

    Boolean matching, checking whether two completely specified Boolean functions are logically equal, is widely used in logic synthesis. It is well known that BDD is a common tool for Boolean matching. The identifiableness of two BDDs' structures means that two Boolean functions are equal. But BDD varies with different variable order. So, before constructing BDDs and checking equivalence, variables m... View full abstract»

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  • Parameter extraction of threshold voltage model of BSIM3V3

    Publication Year: 2001, Page(s):681 - 684
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (237 KB) | HTML iconHTML

    The threshold model is one of the models of BSIM3V3. The authors have investigated the parameter extraction of the threshold model. Both single-bin and multi-bin algorithms are implemented which avoid the parameter redundancy problem. Refined device schemes are designed to support the group extraction strategy. For the single-bin algorithm, the relative error of the extracted values of the paramet... View full abstract»

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  • An x/sin (x) FIR digital filter for DVB-C/DAVIC modulator

    Publication Year: 2001, Page(s):428 - 430
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB) | HTML iconHTML

    This paper proposes a novel 7-tap sin(x)/x correction digital filter suitable for DVB-C/DAVIC modulator, which can compensate the sinc effect of D/A converter. This filter adopts the modified direct form structure, which has high performance as well as smaller chip area. In addition, it adopts an efficient BIST (built in self test) scheme to greatly improve the testability View full abstract»

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  • Study of test approach for IP cores applicable to SOC designs

    Publication Year: 2001, Page(s):612 - 615
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (321 KB) | HTML iconHTML

    A test approach for testing Intellectual Property (IP) analog/mixed-signal cores is presented. The proposed procedure comprises a two-phase test design process: an equivalent fault analysis is carried out in the initial phase, followed by a built-in self-test (BIST) technique based on the weighted sum of selected node voltages. Each phase of the procedure has been validated with example circuits. ... View full abstract»

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