ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549)

23-25 Oct. 2001

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  • ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549)

    Publication Year: 2001
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    Freely Available from IEEE
  • Research on floorplanning

    Publication Year: 2001
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (66 KB)

    Summary form only given. We discuss our recent progress of block placement for floorplanning. We first extended zone refinement to cluster refinement. We then devised an O-tree floorplan representation for efficient and effective floorplan operations. Lately, we explored the relations between floorplan representations, i.e. slicing O-tree, sequence pairs, corner block list, O-tree, and twin binary... View full abstract»

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  • Technology roadmap on SOC testing: issues on SOC testing in DSM era

    Publication Year: 2001
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (66 KB) | HTML iconHTML

    Summary form only given. Deep sub-micron technology is rapidly leading to exceedingly complex, billion- transistor chips. By these technology evolutions, a system is integrated into a chip so called a system-on-a-chip (SOC). In order to bridge the productivity gap between available transistors and the ability to be designed in SOC, higher-level behavioral language and design re-use become more com... View full abstract»

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  • Authors index

    Publication Year: 2001, Page(s):889 - 893
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    Freely Available from IEEE
  • A compact algorithm for placement design using corner block list representation

    Publication Year: 2001, Page(s):146 - 149
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (650 KB) | HTML iconHTML

    Corner Block List (CBL) was recently proposed as an efficient representation of general packing of rectangles. Although the original method is really innovative, there still remains room of improvement. This paper proposes a compact algorithm for placement based on corner block list. By introducing the dummy blocks in CBL, our algorithm can intellective employ dummy blocks in the packing to repres... View full abstract»

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  • The performances comparison between DLL and PLL based RF CMOS oscillators

    Publication Year: 2001, Page(s):827 - 830
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (339 KB)

    In this paper, the comparison of the jitter performances and the spurious tones between DLL (Delay Locked Loop) and PLL based RF CMOS oscillators is produced. An equation which offers the evaluation of the strength of the spurious tones due to the current mismatches in charge pumps of DLL based RF CMOS oscillators is offered. By the jitter performance comparison between the PLL and DLL, some sugge... View full abstract»

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  • Design of mixed-signal circuit for testability

    Publication Year: 2001, Page(s):616 - 619
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (433 KB) | HTML iconHTML

    The test and design for testability methods for each type of block exist but assume a direct access to the block under test. Thus, an additional design for testability structure using boundary scan and mixed-signal test bus is incorporated for effective test application. With this design, separate specialized tests are applied to analog and digital parts, as well as to interconnects. The area over... View full abstract»

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  • Distinguishing variables of Boolean function via distinct subBDDs

    Publication Year: 2001, Page(s):141 - 145
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (426 KB) | HTML iconHTML

    Boolean matching, checking whether two completely specified Boolean functions are logically equal, is widely used in logic synthesis. It is well known that BDD is a common tool for Boolean matching. The identifiableness of two BDDs' structures means that two Boolean functions are equal. But BDD varies with different variable order. So, before constructing BDDs and checking equivalence, variables m... View full abstract»

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  • A novel CMOS quadrature VCO based on symmetrical spiral inductors and differential diodes

    Publication Year: 2001, Page(s):823 - 826
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (293 KB)

    The paper presents a novel method to produce quadrature local oscillating (LO) signals. By using Symmetrical Inductors and Differential Diodes, the circuit has been integrated into a single chip completely. HSPICE simulation results proves it could generate quadrature LO signals with high phase accuracy and good gain match under low power, good phase noise and small area, thus it could be used in ... View full abstract»

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  • Low voltage single-stage amplifier with wide output range

    Publication Year: 2001, Page(s):285 - 288
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (397 KB) | HTML iconHTML

    A single-stage wide output amplifier capable of operating at minimum supply voltage has been described. The simple circuit with low voltage current mirrors is placed between both input differential pair and push-pull output for achieving internal low impedance nodes and minimum supply voltage. This amplifier can be available to work at supply voltage around 1 V for standard CMOS processes View full abstract»

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  • System-on-Chip design

    Publication Year: 2001, Page(s):12 - 17
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (706 KB) | HTML iconHTML

    This tutorial is a general introduction to System-on-Chip (SoC) design. In the paper, we will discuss four areas: first, an overview of SoC including descriptions of the major approaches and motivating factors behind this development. Next, we will briefly summarise key design methodologies, processes and flows. SoC, by its nature, involves embedded software (ESW) in many designs, so we will summa... View full abstract»

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  • The correction of frequency-dependent I/Q mismatches in quadrature receivers by adaptive signal separation

    Publication Year: 2001, Page(s):424 - 427
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (447 KB) | HTML iconHTML

    The I/Q mismatches in a quadrature radio receiver designed for multi-channel reception can be frequency-dependent and limit its image rejection performance to an unacceptable level. In this paper, an adaptive signal-image separation system is proposed to correct the frequency-dependent I/Q mismatches in the digital domain. Simulation results verifying the proposed method are given View full abstract»

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  • Study of test approach for IP cores applicable to SOC designs

    Publication Year: 2001, Page(s):612 - 615
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    A test approach for testing Intellectual Property (IP) analog/mixed-signal cores is presented. The proposed procedure comprises a two-phase test design process: an equivalent fault analysis is carried out in the initial phase, followed by a built-in self-test (BIST) technique based on the weighted sum of selected node voltages. Each phase of the procedure has been validated with example circuits. ... View full abstract»

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  • Parallel behavior-level simulator based on VHDL-AMS [mixed circuit simulation]

    Publication Year: 2001, Page(s):700 - 703
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (325 KB) | HTML iconHTML

    This paper proposes a novel approach that makes use of a software package named parallel virtual machine (PVM), which allows a researcher to use workstations as nodes in a parallel processing environment to perform a large-scale simulation. The parallel scheme is described, and the computational power and cost effectiveness of PVM are demonstrated on the problem of simulating mixed circuits View full abstract»

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  • A modified microprogramming control for FPU

    Publication Year: 2001, Page(s):789 - 792
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (446 KB) | HTML iconHTML

    A novel architecture and control of the FPU LSC87 chip, which is instruction compatible with INTEL 8087 coprocessors, is described. The modified microprogramming control presented here is best suited for complicated processes, including the supporting of 7 floating point numbers and binary or decimal integers, the implementation of IEEE standard 754 floating point arithmetic, as well as the comput... View full abstract»

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  • Improving circuit simulation accuracy by partitioning algorithm

    Publication Year: 2001, Page(s):136 - 140
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB) | HTML iconHTML

    In this paper, error models based on partitioning of matrices are derived for solving a sparse linear system of circuit equations. Better agreement between actual computed results and estimated errors is achieved. It is shown that the algorithm proposed here can improve the accuracy of large circuit simulations View full abstract»

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  • 2.5-Gb/s 0.35-μm CMOS laser-diode driver

    Publication Year: 2001, Page(s):821 - 822
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    A 2.5 Gb/s laser diode driver IC to be used in SDH system has been realized by using a standard 0.35-μm CMOS process. The modulation current is as high as 60 mA and temperature respect is considered. The chip area is 0.9 mm2 View full abstract»

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  • Precise modeling of A/D converter and the macromodel of AD1380

    Publication Year: 2001, Page(s):303 - 306
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (253 KB) | HTML iconHTML

    A precise macromodel for A/D converter is constructed on the basis of relating subfunctional module several key parameters for solving the problem of modeling A/D converter and the macromodel of A/D converter is founded. The method the paper provides can guide the quick and precise modeling of congeneric A/D converters in the board-level design of electronic products while the macromodel is made w... View full abstract»

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  • MOSFET parameters extraction in VDSM ULSI CAD with a parallel-programming strategy

    Publication Year: 2001, Page(s):673 - 676
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (501 KB) | HTML iconHTML

    In this paper, we develop an efficient optimization algorithm for MOSFET parameter extraction in VDSM ULSI circuit design, which combines a search-space smoothing strategy, smoothes a large number of local barriers and makes conventional heuristic searching much more efficient. The experiment was implemented with a parallel programming strategy on a distributed multi-computer system with improved ... View full abstract»

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  • Design of fully differential fourth-order Bessel filter with accurate group delay

    Publication Year: 2001, Page(s):281 - 284
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (254 KB) | HTML iconHTML

    A fully differential R-MOSFET-C fourth-order Bessel active lowpass filter employing passive resistances and current-steering MOS transistors as a variable resistance is proposed. This proposed implementation relies on the tunability of the current-steering MOS transistors operating in the triode region counteracting the concert deviation of resistance in integrated circuit manufacturing technology... View full abstract»

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  • A new on-chip DC-DC voltage down converter for low-power VLSI chip

    Publication Year: 2001, Page(s):244 - 247
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    An on-chip DC-DC voltage down converter (VDC) is proposed. Employing a new reference voltage generator (RVG) and a differential-amplifier-based follower, the architecture of the proposed VDC is simple, and can be fabricated by conventional CMOS technology. For 5 V-to-3 V conversion, the output voltage (Vout) is stabilized within ±0.1% for ±10% variation of supply voltage, and within ... View full abstract»

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  • A study on implementing wavelet transform and FFT with FPGA

    Publication Year: 2001, Page(s):486 - 489
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    This paper shows how to implement the wavelet transform and the Fast Fourier Transform (FFT) with a Field Programmed Gate Array (FPGA). First, it introduces the implementation of the wavelet transform with lattice filters and achieves the FFT with the Coordinate Rotational Digital Computation (CORDIC). Then, the emulation data of the Daubechies D4 & D6 wavelet transforms and the FFT with 16 po... View full abstract»

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  • Performance-driven placement of multi-million-gate circuits

    Publication Year: 2001, Page(s):1 - 11
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1357 KB) | HTML iconHTML

    We survey recent development in placement technology for VLSI layout. In the very deep submicron era, we have to deal with two issues: huge design complexity and wiring-delay dominance of circuit performance. Ever increasing functionality demand and exponentially growing technology capacity together make layout of multi-million-gate circuits everyday work. Because of high-performance requirement a... View full abstract»

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  • 64QAM trellis-decoding with channel state information

    Publication Year: 2001, Page(s):420 - 423
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (306 KB) | HTML iconHTML

    Introduces a modified 64QAM trellis decoding method, which uses channel state information (CSI) in computing the branch metrics. The CSI is obtained by correlating the received channel sounding sequence with the known PN sequence in channel estimation. After the modification, the BER vs. SNR performance has been increased up to 1 dB over multipath channel environment View full abstract»

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  • How to generate tests using semi-formal technique: industrial experiences

    Publication Year: 2001, Page(s):607 - 611
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (731 KB) | HTML iconHTML

    This paper resulted from the successful application of semi-formal test generation techniques on two industrial designs: a block of a new high performance digital signal processors and a block of a new 64-bit processor core. We describe the developed test generation methodology that should be applicable to a wide range of designs View full abstract»

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