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ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549)

23-25 Oct. 2001

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  • ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549)

    Publication Year: 2001
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    Freely Available from IEEE
  • Research on floorplanning

    Publication Year: 2001
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (66 KB)

    Summary form only given. We discuss our recent progress of block placement for floorplanning. We first extended zone refinement to cluster refinement. We then devised an O-tree floorplan representation for efficient and effective floorplan operations. Lately, we explored the relations between floorplan representations, i.e. slicing O-tree, sequence pairs, corner block list, O-tree, and twin binary... View full abstract»

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  • Technology roadmap on SOC testing: issues on SOC testing in DSM era

    Publication Year: 2001
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (66 KB) | HTML iconHTML

    Summary form only given. Deep sub-micron technology is rapidly leading to exceedingly complex, billion- transistor chips. By these technology evolutions, a system is integrated into a chip so called a system-on-a-chip (SOC). In order to bridge the productivity gap between available transistors and the ability to be designed in SOC, higher-level behavioral language and design re-use become more com... View full abstract»

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  • Authors index

    Publication Year: 2001, Page(s):889 - 893
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    Freely Available from IEEE
  • Adiabatic NP-domino circuits

    Publication Year: 2001, Page(s):884 - 887
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB) | HTML iconHTML

    In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuits adopting AC power supply. First, we discuss the algebraic expressions and the corresponding properties of clocked signals. Then, based on summing up the traditional domino circuit design, the design of NP-domino circuits adopting power-clock is proposed in this paper. We carry out PS... View full abstract»

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  • 2.5-Gb/s 0.35-μm CMOS laser-diode driver

    Publication Year: 2001, Page(s):821 - 822
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (242 KB) | HTML iconHTML

    A 2.5 Gb/s laser diode driver IC to be used in SDH system has been realized by using a standard 0.35-μm CMOS process. The modulation current is as high as 60 mA and temperature respect is considered. The chip area is 0.9 mm2 View full abstract»

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  • Study on self-heat effects in integrated circuits with hot-spot and electro-thermal coupling methods

    Publication Year: 2001, Page(s):880 - 883
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB) | HTML iconHTML

    The self-heat effects in integrated circuits have great impact on circuit performance and power consumption. Based on HSPICE circuit simulator and improved Hot-Spot thermal analysis, this paper presents a new fast electro-thermal relaxation method to study the self-heat effects. Given the layout information and the input signal pattern, the developed method may calculate the temperature distributi... View full abstract»

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  • A 3.3-V, 2-GHz CMOS low noise amplifier

    Publication Year: 2001, Page(s):818 - 820
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB) | HTML iconHTML

    A CMOS low noise amplifier is designed based on a narrowband LC-tuned cascode topology. With a standard 0.6 micron CMOS technology, this technique is applied to design a 3.3 V LNA operating at 2 GHz for IMT2000 band application. On-chip inductors have been used. Simulation results show that the LNA is featured with a gain of 18 dB, noise figure of 2.3 dB, IIP3 of -4.9 dBm, power dissipation of 33.... View full abstract»

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  • A new channel routing algorithm based on Steiner minimum tree

    Publication Year: 2001, Page(s):126 - 129
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (437 KB) | HTML iconHTML

    In this article, we propose a new channel routing algorithm based on the Steiner minimum tree for a fixed amount of routing channels. By adding some doglegs and changing the order of routing, the algorithm can sufficiently use the channel resources. Quick and efficient channel routing can be implemented by using this algorithm. A routing sample is also provided View full abstract»

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  • Design of a 11 bit 10Ms/s pipelined A/D converter

    Publication Year: 2001, Page(s):310 - 313
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (198 KB) | HTML iconHTML

    A 11 bit 10Ms/s A/D Converter (ADC) is presented. The converter consists of a five-stage pipelined architecture and adopts the negative redundant digital correction technique to correct errors in the gain and offset. The fully differential circuitry is used to improve the power supply rejection and reduce errors resulting from the charge injection. The ADC is designed in a 0.6um CMOS technology an... View full abstract»

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  • Switching and analog performance of 0.6 volt, 20 nm effective channel length Si ASIC Dual Carrier Field Effect Transistor and three dimensional field effect transistor

    Publication Year: 2001, Page(s):876 - 879
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB) | HTML iconHTML

    Theoretical studies of switching and analog performance of 0.6 volt 20 nm effective channel length Si ASIC of Dual Carrier Field Effect Transistor and Three Dimensional Field Effect Transistors will be presented. It will be shown that these field effect transistors can be fabricated by using mature semiconductor technology for linewidth greater than 130 nm View full abstract»

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  • A 0.18-μm CMOS LNAs with sub-2 dB NF and low power for Bluetooth applications

    Publication Year: 2001, Page(s):815 - 817
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (175 KB) | HTML iconHTML

    A 2.4 GHz low noise amplifier (LNA), intended for use in a Bluetooth receiver, has been designed in a standard 0.18 μm in CMOS process. The amplifier provides a forward gain (s21) of about 25 dB with a noise figure of sub-2 dB, while consuming only 16 mW power with a 1.5 V supply. It has a good linearity, with the IIP3 equal to -8 dBm around View full abstract»

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  • A mixed mode placement algorithm for combined design of macro blocks and standard cells

    Publication Year: 2001, Page(s):122 - 125
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (425 KB) | HTML iconHTML

    A hierarchical automatic placement algorithm for mixed mode placement problems is presented. The so-called mixed mode is a combination of standard cells and macro blocks. The presented algorithm completes the placement at both block level and cell level. In block level, the random cells are firstly partitioned into soft blocks, then a SP (sequence pair) based method (Murata et al, IEEE Trans. CAD,... View full abstract»

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  • Computer aided design of switched-current filters

    Publication Year: 2001, Page(s):94 - 97
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB) | HTML iconHTML

    This paper offers a CAD program, SIFDS (switched current filter design system), which can be used to design Butterworth, Chebyshev and elliptic types of SI filters; each type includes low-pass (LP), high pass (HP), band-pass (BP) and band-elimination (BE) filters, giving a total of 12 kinds of filters. By inputting target filter specifications, this CAD tool can yield the transfer function H(z), s... View full abstract»

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  • Study and design of a 16-bit oversampling Σ-Δ A/D converter

    Publication Year: 2001, Page(s):307 - 309
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (205 KB) | HTML iconHTML

    A 16-bit oversampling Σ - Δ A/D converter is presented. The modulator in the converter is implemented by using 4-order structure; the digital decimation filters are realized with two stage filters: the combed filter and half-band filter. The modulator with 16-bit resolution is achieved in this A/D converter at a oversampling rate of 64 View full abstract»

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  • Testing IP cores with pseudo exhaustive test sets

    Publication Year: 2001, Page(s):740 - 743
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (353 KB) | HTML iconHTML

    Testing core-based SOCs poses a big challenge to test engineers. To test core-based SOCs, an important step is to get test sets for testing cores. Soft cores are usually provided with hardware description languages such as VHDL and Verilog. It is much more difficult to generate test sets at higher level than at logic level. Recently, researchers have made efforts to develop test pattern generation... View full abstract»

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  • Car collision-prevention radar system

    Publication Year: 2001, Page(s):872 - 875
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (342 KB) | HTML iconHTML

    In these years, there is a high rate of car chain-collision accidents on the highways, especially on the expressways. Yet, until recently no good solution to this problem has been worked out. In this paper, an attempt to solve the problem completely is presented, that is, the car-carried range finding radar, which can automatically control the driving speed and keep a given space between the cars View full abstract»

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  • A 1 GHz analog multiplier with shunt-peaked LNA core

    Publication Year: 2001, Page(s):811 - 814
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (235 KB) | HTML iconHTML

    A 1 GHz analog multiplier with a supply of 1.2 V is implemented with a 0.6 micron DPDM standard CMOS technology of CSMC, China. With a shunt-peaked, low noise amplifier (LNA) core, the proposed multiplier features with IIP3 of 6.3 dBm (for mixer application), conversion gain of 10 dB and noise figure of 18 dB with a power consumption of 22 mW. Several design techniques have been adopted to achieve... View full abstract»

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  • CEP: a clock-driven ECO placement algorithm for standard-cell layout

    Publication Year: 2001, Page(s):118 - 121
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (542 KB) | HTML iconHTML

    Incremental placement or ECO (engineer change order) placement is a new field in VLSI layout to meet the demand of high performance design. In this paper, a novel clock-driven ECO placement algorithm, CEP, is presented for standard cell layout design. It considers clock skew information in the placement stage, modifies the positions of cells locally to make better preparation for the clock routing... View full abstract»

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  • Low voltage single-stage amplifier with wide output range

    Publication Year: 2001, Page(s):285 - 288
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (397 KB) | HTML iconHTML

    A single-stage wide output amplifier capable of operating at minimum supply voltage has been described. The simple circuit with low voltage current mirrors is placed between both input differential pair and push-pull output for achieving internal low impedance nodes and minimum supply voltage. This amplifier can be available to work at supply voltage around 1 V for standard CMOS processes View full abstract»

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  • The design of a novel low-power and high-precision voltage testing circuit

    Publication Year: 2001, Page(s):637 - 640
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (299 KB) | HTML iconHTML

    This paper presents the design of a novel low-power and high-precision voltage testing circuit. The circuit consists of a temperature-insensitive reference voltage generator and a voltage follower to eliminate the loading effect. The circuit has been fabricated in 0.8 μm CMOS technology and its performance has been measured, which shows that the circuit functions are consistence with the theore... View full abstract»

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  • How to generate tests using semi-formal technique: industrial experiences

    Publication Year: 2001, Page(s):607 - 611
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (731 KB) | HTML iconHTML

    This paper resulted from the successful application of semi-formal test generation techniques on two industrial designs: a block of a new high performance digital signal processors and a block of a new 64-bit processor core. We describe the developed test generation methodology that should be applicable to a wide range of designs View full abstract»

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  • A new modeling technique based on the ANN and DOE for interconnects

    Publication Year: 2001, Page(s):91 - 93
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (257 KB) | HTML iconHTML

    This paper mainly introduces a new method for building interconnect macro-models based on the multilayer feed-forward artificial neural network (ANN) and design of experiment (DOE). The test examples show that making use of orthogonal tables to arrange the selection of training data can obviously improve the efficiency for building macro-models of interconnect networks in comparison with training ... View full abstract»

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  • Boolean matching algorithm based on the perfect matching of the bipartite graph

    Publication Year: 2001, Page(s):150 - 154
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB) | HTML iconHTML

    This paper presents an improved Boolean matching algorithm based on the perfect matching of the bipartite graph. By transforming the mapping between Boolean variables into the problem of the perfect matching of the bipartite graph, this improved algorithm can overcome the shortcoming of the original algorithm, i.e., lengthy computation time caused by the excessive mapping terms. It is shown throug... View full abstract»

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  • Precise modeling of A/D converter and the macromodel of AD1380

    Publication Year: 2001, Page(s):303 - 306
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (253 KB) | HTML iconHTML

    A precise macromodel for A/D converter is constructed on the basis of relating subfunctional module several key parameters for solving the problem of modeling A/D converter and the macromodel of A/D converter is founded. The method the paper provides can guide the quick and precise modeling of congeneric A/D converters in the board-level design of electronic products while the macromodel is made w... View full abstract»

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