By Topic

Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on

Date 4-8 Nov. 2001

Filter Results

Displaying Results 1 - 25 of 100
  • IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers [Front Cover and Table of Contents]

    Publication Year: 2001
    Save to Project icon | Request Permissions | PDF file iconPDF (589 KB)  
    Freely Available from IEEE
  • Static scheduling of multi-domain memories for functional verification

    Publication Year: 2001 , Page(s): 2 - 9
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (849 KB) |  | HTML iconHTML  

    The presence of multiple clock domains presents significant challenges for large parallel verification systems such as parallel simulators and logic emulators that model both design logic and memory. Specifically, multiple asynchronous design clocks make it difficult to verify that design hold times are met during memory model execution and causality along memory data/control paths is preserved during signal communication. We describe new scheduling heuristics for memory-based designs with multiple asynchronous clock domains that are mapped to parallel verification systems. The scheduling approach scales to an unlimited number of clock domains and converges quickly to a feasible solution if one exists. It is shown that when the technique is applied to an FPGA-based emulator containing 48MB of SRAM, evaluation fidelity. is maintained and increased verification performance is achieved for large, memory-intensive circuits with multiple asynchronous clock domains. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A simulation-based method for the verification of shared memory in multiprocessor systems

    Publication Year: 2001 , Page(s): 10 - 17
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (769 KB)  

    As processor architectural complexity increases, greater effort must be focused on functional verification of the chip as a component of the system. Multiprocessor verification presents a particular challenge in terms of both difficulty and importance. While formal methods have made significant progress in the validation of coherence protocols, these methods are not always practical to apply to the structural implementation of a complex microprocessor. This paper describes a simulation-based approach to modeling and checking the shared-memory properties of the Alpha architecture by using a directed acyclic graph to represent memory-access orderings. The resulting tool is integrated with a simulation model of an Alpha implementation, allowing the user to verify aspects of the implementation with respect to the overall architectural specification. Both an implementation-independent and an implementation-specific version of the tool are discussed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Predicting the performance of synchronous discrete event simulation systems

    Publication Year: 2001 , Page(s): 18 - 23
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (814 KB) |  | HTML iconHTML  

    In this paper we propose a model to predict the performance of synchronous discrete event simulation. The model considers parameters including the number of active objects per cycle, event execution granularity and communication cost. We, derive a single formula that predicts the performance of synchronous simulation. We have benchmarked several VHDL circuits on SGI Origin 2000. The benchmark results show that the prediction model explains more than 90% of parallel simulation execution time. We also measure the effect of computation granularity over performance. The benchmark results show that although higher granularity can have better speedup because of dominance of computation over communication, the computational granularity cannot overshadow the inherent synchronization cost. This model can be used to predict the speed-up expected for synchronous simulation, and to decide whether it is worthwhile to use synchronous simulation before actually implementing it. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • System-level exploration for Pareto-optimal configurations in parameterized systems-on-a-chip

    Publication Year: 2001 , Page(s): 25 - 30
    Cited by:  Papers (3)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (741 KB) |  | HTML iconHTML  

    Provides a technique for efficiently exploring the configuration space of a parameterized system-on-a-chip (SOC) architecture to find all Pareto-optimal configurations. These configurations represent the range of meaningful power and performance tradeoffs that are obtainable by adjusting parameter values for a fixed application mapped onto the SOC architecture. The approach extensively prunes the potentially large configuration space by taking advantage of parameter dependencies. The authors have successfully incorporated the technique into the parameterized SOC tuning environment (Platune) and applied it to a number of applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • System level design with SPADE: an M-JPEG case study

    Publication Year: 2001 , Page(s): 31 - 38
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (897 KB)  

    Presents and evaluates the SPADE (System level Performance Analysis and Design space Exploration) methodology through an illustrative case study. SPADE is a method and tool for architecture exploration of heterogeneous signal processing systems. In this case study we start from an M-JPEG application and use SPADE to evaluate alternative multiprocessor architectures for implementing this application. SPADE follows the Y-chart paradigm for system level design; application and architecture are modeled separately and mapped onto each other in an explicit design step. SPADE permits architectures to be modeled at an abstract level using a library of generic building blocks, thereby reducing the cost of model construction and simulation. The case study shows that SPADE supports efficient exploration of candidate architectures; models can be easily constructed, modified and simulated in order to quickly evaluate alternative system implementations. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • NetBench: a benchmarking suite for network processors

    Publication Year: 2001 , Page(s): 39 - 42
    Cited by:  Papers (41)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (442 KB) |  | HTML iconHTML  

    Introduces NetBench, a benchmarking suite for network processors. NetBench contains a total of 9 applications that are representative of commercial applications for network processors. These applications are from all levels of packet processing; small, low-level code fragments as well as large application level programs are included in the suite. Using SimpleScalar simulator we study the NetBench programs in detail and characterize the network processor workloads. We also compare key characteristics such as instructions per cycle, instruction distribution, branch prediction accuracy, and cache behavior with the programs from MediaBench. Although the architectures are similar for MediaBench and NetBench suites, we show that these workloads have significantly different characteristics. Hence a separate benchmarking suite for network processors is a necessity. Finally, we present performance measurements from Intel IXP1200 Network Processor to show how NetBench can be utilized. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis of substrate thermal gradient effects on optimal buffer insertion

    Publication Year: 2001 , Page(s): 44 - 48
    Cited by:  Papers (10)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (643 KB) |  | HTML iconHTML  

    Studies the effects of the substrate thermal gradients on the buffer insertion techniques. Using a non-uniform temperature-dependent distributed RC interconnect delay model, the buffer insertion problem is analyzed and design guidelines are provided to ensure the near-optimality of the signal performance in the presence of the thermal gradients. In addition, the effect of temperature-dependent driver resistance on the buffer insertion is studied. Experimental results show that neglecting thermal gradients in the substrate and the interconnect lines can result in non-optimal solutions when using standard buffer insertion techniques and that these effects intensify with technology scaling. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints

    Publication Year: 2001 , Page(s): 49 - 56
    Cited by:  Papers (21)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (932 KB) |  | HTML iconHTML  

    Buffer insertion and wire sizing are critical in deep submicron VLSI design. This paper studies the problem of constructing routing trees with simultaneous buffer insertion and wire sizing in the presence of routing and buffer obstacles. No previous algorithms consider all these factors simultaneously. Previous dynamic programming based algorithm is first extended to solve the problem. However, with the size of routing graph increasing and with wire sizing taken into account, the time and space requirement increases enormously. Then a new approach is proposed to formulate the problem as a series of graph problems. The routing tree solution is obtained by finding shortest paths in a series of graphs. In the new approach, wire sizing can be handled almost without any additional time and space requirement, Moreover, the time and space requirement is only polynomial in terms of the size of routing graph. Our algorithm differs from traditional dynamic programming, and is capable of addressing the problem of inverter insertion and sink polarity. Both theoretical and experimental results show that the graph-based algorithm outperforms the DP-based algorithm by a large margin. We also propose a hierarchical approach to construct routing tree for a large number of sinks. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Bus encoding to prevent crosstalk delay

    Publication Year: 2001 , Page(s): 57 - 63
    Cited by:  Papers (90)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (636 KB) |  | HTML iconHTML  

    The propagation delay across long on-chip buses is increasingly becoming a limiting factor in high-speed designs. Crosstalk between adjacent wires on the bus may create a significant portion of this delay. Placing a shield wire between each signal wire alleviates the crosstalk problem but doubles the area used by the bus, an unacceptable consequence when the bus is routed using scarce top-level metal resources. Instead, we propose to employ data encoding to eliminate crosstalk delay within a bus. This paper presents a rigorous analysis of the theory behind "self-shielding codes", and gives the fundamental theoretical limits on the performance of codes with and without memory. Specifically, we find that a 32-bit bus can be encoded with 40 wires using a code with memory or 46 wires with a memoryless code, in comparison to the 63 wires required with simple shielding. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Behavioral modeling of analog circuits by wavelet collocation method

    Publication Year: 2001 , Page(s): 65 - 69
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (511 KB) |  | HTML iconHTML  

    In this paper, we develop a wavelet collocation method with nonlinear companding for behavioral modeling of analog circuits. To construct the behavioral models, the circuit is first partitioned into building blocks and the input-output function of each block is then approximated by wavelets. As the blocks are mathematically represented by sets of simple wavelet basis functions, the computation cost for the behavioral simulation is significantly reduced. The proposed method presents several merits compared with those conventional techniques. First, the algorithm for expanding input-output functions by wavelets is a general-purpose approach, which can be applied in automatically modeling of different analog circuit blocks with different structures. Second, both the small signal effect and the large signal effect are modeled in a unified formulation, which eases the process of modeling and simulation. Third, a nonlinear companding method is developed to control the modeling error distribution, To demonstrate the promising features of the proposed method, a 4th order switched-current filter is employed to build the behavioral model. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Simulation-based automatic generation of signomial and posynomial performance models for analog integrated circuit sizing

    Publication Year: 2001 , Page(s): 70 - 74
    Cited by:  Papers (22)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (593 KB) |  | HTML iconHTML  

    This paper presents a method to automatically generate posynomial response surface models for the performance parameters of analog integrated circuits. The posynomial models enable the use of efficient geometric programming techniques for circuit sizing and optimization. To avoid manual derivation of approximate symbolic equations and subsequent casting to posynomial format, techniques from design of experiments and response surface modeling in combination with SPICE simulations are used to generate signomial and posynomial models in an automatic way. Attention is paid to estimating the relative 'goodness-of-fit' of the generated models. Experimental results allow one to assess both the quality of the generated models as well as the strengths and the limitations of the presented approach. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method

    Publication Year: 2001 , Page(s): 75 - 80
    Cited by:  Papers (12)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (562 KB) |  | HTML iconHTML  

    The soaring clocking frequency and integration density demand robust and stable power delivery to support tens of millions of transistors switching. To ensure the design quality of power delivery, extensive transient power grid simulations need to be performed during design process. However, the traditional circuit simulation engines are not scaled as well as the complexity of power delivery, as a result, it often takes a long runtime and huge memory requirement to simulate a medium size power grid circuit. We develop and present a new efficient transient simulation algorithm for power distribution. The proposed algorithm, TLM-ADI (transmission-line-modeling alternatingdirection-implicit), first models the power delivery structure as transmission line mesh structure, then solves the transient MNA matrices by the alternating-direction-implicit method. The proposed algorithm, with linear runtime and memory requirement, is also unconditionally stable which ensures that the time-step is not limited by any stability requirement. Extensive experimental results show that the proposed algorithm is not only orders of magnitude faster than SPICE but also extremely accurate. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Sequential SPFDs

    Publication Year: 2001 , Page(s): 84 - 90
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (582 KB) |  | HTML iconHTML  

    SPFDs are a mechanism to express flexibility in Boolean networks. Introduced by Yamashita et al. in the context of FPGA synthesis [1996], they were extended later to general combinational networks. We introduce the concept of sequential SPFDs and provide an algorithm to compute them based on a partition of the state bits. The SPFDs, of each component in the partition are used to generate equivalence classes of states. We provide a formal relation between the resulting state classification and the equivalence classes produced by classical state minimization of completely specified machines. The SPFDs, associated with the state bits can be applied for re-encoding the state space. For this, we give an algorithm to re-synthesize the sequential circuit using sequential SPFDs and the new state re-encoding. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On the optimization power of redundancy addition and removal techniques for sequential circuits

    Publication Year: 2001 , Page(s): 91 - 94
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (294 KB) |  | HTML iconHTML  

    This paper attempts to determine the capabilities of existing redundancy addition and removal (SRAR) techniques for logic optimization of sequential circuits. To this purpose, we compare this method with the retiming and resynthesis (RaR) techniques. For the RaR case, the set of possible transformations has been established by relating them to STG transformations by other authors. Following these works, we first formally demonstrate that logic transformations provided by RaR are covered by SRAR as well. Then, we also show that SRAR is able to identify transformations that cannot be found by RaR. This way we prove the higher potential of the sequential redundancy addition and removal techniques over the retiming and resynthesis techniques. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Placement driven retiming with a coupled edge timing model

    Publication Year: 2001 , Page(s): 95 - 102
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (812 KB)  

    Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear whether the predicted performance improvement will still be valid after placement has been performed. This paper presents a new retiming algorithm using a highly accurate timing model taking into account the effect of retiming on capacitive loads of single wires as well as fanout systems. We propose the integration of retiming into a timing-driven standard cell placement environment based on simulated annealing. Retiming is used as an optimization technique throughout the whole placement process. The experimental results show the benefit of the proposed approach. In comparison with the conventional design flow based on standard FEAS (Leiserson and Saxe, J. VLSI and Computer Sys., pp. 41-67, 1983; and Algorithmica vol. 6, no 1, pp. 5-35, 1991.), our approach achieved an improvement in cycle time of up to 34% and 17% on the average. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Solution of parallel language equations for logic synthesis

    Publication Year: 2001 , Page(s): 103 - 110
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (845 KB) |  | HTML iconHTML  

    The problem of designing a component that, combined with a known part of a system, conforms to a given overall specification arises in several applications ranging from logic synthesis to the design of discrete controllers. We cast the problem as solving abstract equations over languages. Language equations can be defined with respect to several language composition operators such as synchronous composition, /spl middot/, and parallel composition, /spl square/; conformity can be checked by language containment. In this paper, we address parallel language equations. Parallel composition arises in the context of modeling delay-insensitive processes and their environments. The parallel composition operator models an exchange protocol by which an input is followed by an output after a finite exchange of internal signals. It abstracts a system with two components with a single message in transit, such that at each instance either the components exchange messages or one of them communicates with its environment, which submits the next external input to the system only after the system has produced an external output in response to the previous input. We study the most general solutions of the language equation A/spl square/X/spl sube/C, and define the language operators needed to express them. Then we specialize such equations to languages associated with important classes of automata used for modeling systems, e.g., regular languages and FSM languages. In particular, for A/spl square/X/spl sube/C, we give algorithms for computing: the largest FSM language solution, the largest complete solution, and the largest solution whose composition with A yields a complete FSM language. We solve also FSM equations under bounded parallel composition. In this paper, we give concrete algorithms for computing such solutions, and state and prove their correctness. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • CALiBeR: a software pipelining algorithm for clustered embedded VLIW processors

    Publication Year: 2001 , Page(s): 112 - 118
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (880 KB) |  | HTML iconHTML  

    In this paper, we describe a software pipelining framework, CALiBeR (cluster aware load balancing retiming algorithm), suitable for compilers targeting clustered embedded VLIW processors. CALiBeR can be effectively used by embedded system designers to explore different code optimization alternatives, i.e. it can assist the generation of high-quality customized retiming solutions for desired program memory size and throughput requirements, while minimizing register pressure. An extensive set of experimental results is presented, considering several representative benchmark loop kernels and a wide variety of clustered datapath configurations, demonstrating that our algorithm compares favorably with one of the best state-of-the-art algorithms, achieving up to 50% improvement in performance and up to 47% improvement in register requirements. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Software-assisted cache replacement mechanisms for embedded systems

    Publication Year: 2001 , Page(s): 119 - 126
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (880 KB) |  | HTML iconHTML  

    We address the problem of improving cache predictability and performance in embedded systems through the use of software-assisted replacement mechanisms. These mechanisms require additional software controlled state information that affects the cache replacement decision. Software instructions allow a program to kill a particular cache element, i.e. effectively make the element the least recently used element, or keep that cache element, i.e. the element will never be evicted. We prove basic theorems that provide conditions under which kill and keep instructions can be inserted into program code, such that the resulting performance is guaranteed to be as good as or better than the original program run using the standard LRU policy. We developed a compiler algorithm based on the theoretical results that, given an arbitrary program, determines when to perform software-assisted replacement, i.e., when to insert either a kill or keep instruction. Empirical evidence is provided that shows that performance and predictability (worst-case performance) can be improved for many programs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Instruction generation for hybrid reconfigurable systems

    Publication Year: 2001 , Page(s): 127 - 130
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (460 KB) |  | HTML iconHTML  

    We present an algorithm for simultaneous template generation and matching. The algorithm profiles the graph and iteratively contracts edges to create the templates. The algorithm is general and can be applied to any type of graph, including directed graphs and hypergraphs. We discuss how to target the algorithm towards the novel problem of instruction generation and selection for a hybrid (re)configurable systems. In particular, we target the strategically programmable system, which embeds complex computational units like ALUs, IP blocks, etc. into a configurable fabric. We argue that an essential compilation step for these systems is instruction generation, as it is needed to specify the functionality of the embedded computational units. Additionally, instruction generation can be used to create soft macros tightly sequenced pre-specified operations placed in the configurable fabric. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Interconnect resource-aware placement for hierarchical FPGAs

    Publication Year: 2001 , Page(s): 132 - 136
    Cited by:  Papers (3)  |  Patents (27)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (708 KB) |  | HTML iconHTML  

    Utilizes Rent's rule as an empirical measure for efficient clustering and placement of circuits on hierarchical FPGAs. We show that careful matching of design complexity and architecture resources of hierarchical FPGAs can have a positive impact on the overall device area. We propose a circuit placement algorithm based on Rent's parameter and show that our clustering and placement techniques can improve the overall device routing area by as much as 21% for the same array size, when compared to a state-of-art FPGA placement and routing tool. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A router for symmetrical FPGAs based on exact routing density evaluation

    Publication Year: 2001 , Page(s): 137 - 143
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (757 KB) |  | HTML iconHTML  

    This paper presents a new performance and routability driven routing algorithm for symmetrical array based field-programmable gate arrays (FPGAs). A key contribution of our work is to overcome one essential limitation of the previous routing algorithms: inaccurate estimations of routing density which were too general for symmetrical FPGAs. To this end, we derive an exact routing density calculation that is based on a precise analysis of the structure (switch block) of symmetrical FPGAs, and utilize it consistently in global and detailed routings. With an introduction of the proposed accurate routing metrics, we design a new routing algorithm called a cost-effective net-decomposition based routing which is fast, and yet produces remarkable routing results in terms of both mutability and path/net delays. We performed an extensive experiment to show the effectiveness of our algorithm based on the proposed cost metrics. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs

    Publication Year: 2001 , Page(s): 144 - 151
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (881 KB) |  | HTML iconHTML  

    Incremental physical CAD is encountered frequently in the so-called engineering change order (ECO) process in which design changes are made typically late in the design process in order to correct logical and/or technological problems in the circuit. As far as routing is concerned, in order to capitalize on the enormous resources and time already spent on routing the circuit, and to meet time-to-market requirements, it is desirable to re-route only the ECO-affected portion of the circuit, while minimizing any routing changes in the much larger unaffected part of the circuit. Incremental re-routing also needs to be fast and to effectively use available routing resources. We develop a complete incremental routing methodology for FPGAs using a novel approach called bump and refit (B&R). We significantly extend this concept to global and detailed incremental routing for FPGAs with complex switchboxes such as those in Lucent's ORCA and Minx's Virtex series. We also introduce new concepts such as B&R cost estimation during global routing, and determination of the optimal subnet set to bump for each bumped net, which we obtain using an efficient dynamic programming formulation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Area minimization of power distribution network using efficient nonlinear programming techniques

    Publication Year: 2001 , Page(s): 153 - 157
    Cited by:  Papers (32)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1214 KB) |  | HTML iconHTML  

    This paper deals with area minimization of power distribution networks for VLSIs. A new algorithm based on efficient nonlinear programming techniques is presented to solve this problem. Experimental results prove that this algorithm has achieved the objectives of minimizing the area of power/ground networks with higher speeds. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Compact modeling and SPICE-based simulation for electrothermal analysis of multilevel ULSI interconnects

    Publication Year: 2001 , Page(s): 165 - 172
    Cited by:  Papers (27)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (845 KB) |  | HTML iconHTML  

    Presents both compact analytical models and fast SPICE based 3-D electro-thermal simulation methodology to characterize thermal effects due to Joule heating in high performance Cu/low-k interconnects under steady-state and transient stress conditions. The results agree with experimental data and those using finite element (FE) thermal simulations (ANSYS). The effect of vias, as additional heat sinking paths to alleviate the temperature rise in the metal wires, is included in the analysis to provide more accurate and realistic thermal diagnosis. It shows that the effectiveness of vias in reducing the temperature rise in interconnects is highly dependent on the via separation and the dielectric materials used. The analytical model is then applied to estimate the temperature distribution in multi-level interconnects. We discuss the possibility that, under the impact of thermal effects, the performance improvement expected from the use of low-k dielectric materials may be degraded. Furthermore, thermal coupling between wires is evaluated and found to be significant. Finally, the impact of metal wire aspect ratio on interconnect thermal characteristics is discussed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.