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Integrated Circuits and Systems Design, 2001, 14th Symposium on.

Date 15-15 Sept. 2001

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Displaying Results 1 - 25 of 39
  • Symposium on Integrated Circuits and Systems Design

    Publication Year: 2001
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    Freely Available from IEEE
  • Using the CAN protocol and reconfigurable computing technology for Web-based smart house automation

    Publication Year: 2001 , Page(s): 38 - 43
    Cited by:  Papers (5)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB) |  | HTML iconHTML  

    This paper presents the hardware implementation of a multiplatform control system for house automation using FPGAs. Such a system belongs to a domain usually named domotics or smart house systems. The approach combines hardware and software technologies. The system is controlled through the Internet and the home devices being connected use the CAN control protocol. Users can remotely control their houses using a Web browser (client). Locally, instructions received from the client are translated by the server, which distributes the commands to the domestic appliances. The implemented system has the following characteristics, which distinguish it from existing approaches: (i) the client interface is automatically updated; (ii) a standard communication protocol (CAN) is used in the hardware implementation, providing reliability and error control; (iii) new appliances are easily inserted in the system; (iv) system security is provided by user authentication; and (v) user rights can be set up by an administration interface. View full abstract»

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  • Author index

    Publication Year: 2001 , Page(s): 237
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    Freely Available from IEEE
  • A simplified methodology for the extraction of the ACM MOST model parameters

    Publication Year: 2001 , Page(s): 136 - 141
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB) |  | HTML iconHTML  

    The ACM model is a powerful tool for the simulation of MOS transistors. Unlike most of the available models, it presents simple and precise equations, allied to a small number but meaningful physical parameters. This paper presents a simplified methodology for extracting the parameters of the ACM model. Unlike usual methods for device characterization, which require the availability of expensive equipment, this methodology is based on simulation. Simple and low cost, it can be reproduced easily by those who plan to use the ACM model but do not know its parameters for a given process. In this work, the ACM parameters were extracted from the BSIM 3 parameters available for a 0.8 μm technology View full abstract»

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  • A 3-V 12-bit second order sigma-delta modulator design in 0.8-μm CMOS

    Publication Year: 2001 , Page(s): 124 - 129
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB) |  | HTML iconHTML  

    This paper examines the design and simulation of a 12-bit sigma-delta modulator that operates from a single 3-V power supply. The proposed modulator has been designed with fully-differential switched-capacitor integrators implemented with folded-cascode operational amplifiers. The main feature of the designed modulator is its simplicity. It shows that it is possible to design a precise modulator of moderate Signal-to-Noise Ratio (SNR) using simple circuits, which do not require precise component matching and high precision components or trimming. The modulator achieves a SNR higher than 74 dB for all the simulated cases with an oversampling ratio of 128 and an oversampling frequency of 2.56 MHz. The modulator was designed in a 0.8-μm CMOS technology and it measures 560 μm × 680 μm View full abstract»

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  • An environment to aid the synthesis of three-phase analogue waveform using AHDL

    Publication Year: 2001 , Page(s): 142 - 147
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB) |  | HTML iconHTML  

    This paper presents a synthesis tool that was developed for generating analogue signals using only digital resources. With the specification at the equation level, the corresponding specification in hardware description language was obtained for a certain analogue signal. The tool developed in C language works with the analogue function, which is implemented by transforming it in a file with the extension TDF, that is the input for AHDL (Altera Hardware Description Language). Using the Max+Plus II project environment, the file obtained was synthesized at the logic gate level, in order to be implemented in a FPGA. Analogue waveforms of practical use, for instance, sine, sigmoid and Gaussian, were modeled with different amounts of bits, synthesized and implemented. Tests show the precision and the efficiency of the developed tool. The waveforms were obtained in the MatLab program and then visualized in a digital oscilloscope View full abstract»

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  • Data encryption in an Electronic Ballot Box

    Publication Year: 2001 , Page(s): 156 - 160
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (376 KB) |  | HTML iconHTML  

    Brazilian Elections rely on an Electronic Ballot Box (EBB). It is based on a PC motherboard, containing a small keypad and a LCD display which shows messages and candidate's pictures. One of the main issues in the voting process is security against fraud. We describe here the implementation of IDEA data encryption algorithm in hardware in order to improve its security. The algorithm was described in VHDL and synthesized in a FPGA View full abstract»

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  • Pipelined fast 2D DCT architecture for JPEG image compression

    Publication Year: 2001 , Page(s): 226 - 231
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB) |  | HTML iconHTML  

    This paper presents the architecture and the VHDL design of a Two Dimensional Discrete Cosine Transform (2-D DCT) for JPEG image compression. This architecture is used as the core of a JPEG compressor and is the critical path in JPEG compression hardware. The 2-D DCT calculation is made using the 2-D DCT separability property, such that the whole architecture is divided into two I-D DCT calculations by using a transpose buffer. These parts are described in this paper, with an architectural discussion and the VHDL synthesis results as well. The 2-D DCT architecture uses 4,792 logic cells of one Altera Flex10kE FPGA and reaches an operating frequency of 12.2 MHz. One input block with 8×8 elements of 8 bits each is processed in 25.2 μs and the pipeline latency is 160 clock cycles View full abstract»

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  • System-level object-orientation in the specification and validation of embedded systems

    Publication Year: 2001 , Page(s): 8 - 13
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB) |  | HTML iconHTML  

    The main aim of this paper is to present how the Unified Modeling Language (UML) can be used as the notation to specify the requirements of an embedded system. By, using a relatively small, but real, system (a supervision application) as a running example, the paper illustrates the design flow that can be followed during the analysis phase of complex control applications. To assure the continuous mapping of the models, the authors propose some guidelines to transform the use case diagrams into a single object diagram, which is the main diagram for the next development phases (design and implementation). The Java programming language is used for developing a system's prototype, to allow the system's validation by the customers View full abstract»

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  • Communication architectures for system-on-chip

    Publication Year: 2001 , Page(s): 14 - 19
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB) |  | HTML iconHTML  

    The analysis of the communication architecture and its associated synthesis process has grown in importance in the era of System-On-Chip (SoC) devices, since one is moving towards more complex systems, made by several processing elements (cores), with heterogeneous behavior. In many cases, the choice for a communication architecture can be the most crucial factor to meet design constraints. This goal of this work is to define and implement algorithms devoted to analyzing and selecting those communication architectures that better match the user defined system constraints, in an integrated design environment View full abstract»

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  • Jale3D-platform-independent IC/MEMS layout edition tool

    Publication Year: 2001 , Page(s): 174 - 179
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (824 KB) |  | HTML iconHTML  

    This paper describes the Jale3D, a tool developed as part of the Cave Framework. The main features of the tool are the edition and the visualization of the layout information from both integrated circuits (ICs) and micro-electromechanical systems (MEMS). The use of the Virtual Reality Modeling Language as a way to create 3D models of integrated circuits and MEMS is also presented View full abstract»

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  • An automated tool for analysis and design of MVL digital circuits

    Publication Year: 2001 , Page(s): 52 - 57
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (968 KB) |  | HTML iconHTML  

    In the development of logical circuits projects in Multivalued Logic, it is necessary to obtain the result of logical expressions that sometimes are very large and complex. A software called ELOmv, that is capable of calculating the truth-table for expressions in ternary or quaternary level with even three variables of entry is presented. The non-classical algebra of MVL based on Post algebra, used in this work is shown, as well as the operators and the synthesis of the logical functions. This software is a tool that can be used in a future work in which synthesis and simplification of logical functions will be performed View full abstract»

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  • A Petri net based approach for hardware/software partitioning

    Publication Year: 2001 , Page(s): 72 - 77
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (552 KB) |  | HTML iconHTML  

    Co-design methodologies have arisen for supporting the development of digital systems composed of mixed hardware/software. Partitioning is performed by co-design tools for splitting the functionality of the original system among its components. In this paper, a partitioning approach based on a Petri net intermediate format is proposed. The new model will substitute the one currently adopted in the PISH co-design system. The main advantages of such a model are having more precise metrics and becoming independent of the specification language View full abstract»

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  • Extending sequencing graphs for reconfigurable applications modeling

    Publication Year: 2001 , Page(s): 161 - 166
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (456 KB) |  | HTML iconHTML  

    This paper introduces an extension to the sequencing graphs used in traditional high-level synthesis. The reconfigurable sequencing graph is a supergraph that includes reconfiguration steps indicating when and what must be changed in a configuration. In addition, the RSG allows defining the kind of reconfiguration necessary to implement an application. With the RSG, it is also possible to determine in which programmability classes the architecture is classified. Modeling with RSG is independent of technology, because it works in high-level of abstraction, but it can include physical characteristics, in order to better determine the transformations in the reconfiguration graph View full abstract»

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  • A repartitioning and HW/SW partitioning algorithm to the automatic design space exploration in the co-synthesis of embedded systems

    Publication Year: 2001 , Page(s): 85 - 90
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (568 KB) |  | HTML iconHTML  

    Presents a co-synthesis algorithm that combines. repartitioning and HW/SW partitioning of the processes in a system specification to provide an efficient design space exploration strategy. The algorithm is defined on a partial order based Model (POM)., which is an alternative to model concurrency at a high level of abstraction and has a concise symbolic representation, mainly for systems with a high degree of parallelism, as well as allowing the use of efficient reachability analysis techniques based on partial order reductions. Our repartitioning algorithm generates a partitioning tree. where the possible partitions of the processes in a specification are represented in a systematic way, according to the communication among them. The HW/SW partitioning algorithm is applied on these possible partitionings and will select the one that minimizes the communication cost between the partitions. In this paper. we present the repartitioning, HW/SW partitioning and performance/cost estimates algorithms and how they are used in the design space exploration strategy. The reported experimental results show the efficiency., when compared with related works, and practicability of our co-synthesis algorithms View full abstract»

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  • IDCT design for JPEG decompression in an electronic ballot box

    Publication Year: 2001 , Page(s): 232 - 236
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    This paper describes the design of a inverse discrete cosine transform (IDCT) to decompress JPEG images. The target application is the decompression of monocromatic photos of candidates in the Brazilian Electronic Ballot Box. The goals is to develop a constrained implementation which targets a XC4010 FPGA. It is based on the application of two 1-D IDCTs using a local memory as buffer. The design resulted in around two hundred logic cells for a two-pass IDCT, which was implemented and tested in the Xilinx demo board View full abstract»

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  • Adaptive systems-on-chip: architectures, technologies and applications

    Publication Year: 2001 , Page(s): 2 - 7
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (616 KB) |  | HTML iconHTML  

    The fast technological development in Very Large Scale Integration (VLSI) has enabled chip-designers to integrate complete electronic systems, formerly built of several separate chips, onto one single piece of silicon. These Systems-on-Chip (SoCs) introduce a set of various challenges for their interdisciplinary microelectronic implementation, from system theory (application) level over efficient CAD methods to suitable technologies. Important aspects for the industry are the flexibility and adaptivity of SoCs, which can be realized by integrating reconfigurable hardware parts on different granularities into Configurable Systems-on-Chip (CSoCs). The paper describes the major challenges and first approaches in architecture, design and application of application-specific adaptive SoCs, e.g. in digital baseband processing for future mobile radio devices View full abstract»

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  • An integrated high-level test synthesis algorithm for built-in self-testable designs

    Publication Year: 2001 , Page(s): 115 - 121
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (616 KB) |  | HTML iconHTML  

    Describes a high-level test synthesis algorithm for operation scheduling and data path allocation. It generates highly self-testable data path design while maximizing the sharing of test registers, which means only a small number of registers is modified for BIST. The algorithm also produces design with high test concurrency, thereby decreasing test time. In the approach, module allocation is guided by a testability balance technique. Register allocation is achieved by an incremental sharing measurement which chooses allocation steps that result in large increases in the sharing degrees of registers. Scheduling, on other hand, is carried out by rescheduling transformations which change the default scheduling to improve testability. With a variety of benchmarks, we demonstrate the advantage of our approach compared with other conventional approaches View full abstract»

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  • Analog circuit design using graded-channel SOI nMOSFETs

    Publication Year: 2001 , Page(s): 130 - 135
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB) |  | HTML iconHTML  

    An extended study of analog circuit design using Graded-Channel Silicon-On-Insulator MOSFETs in comparison to conventional fully-depleted transistors is performed. The performances of a single-transistor operational transconductance amplifier implemented using Graded-Channel (GC) and conventional fully-depleted SOI nMOSFETs are compared. Improvements in the DC gain and unity-gain frequency resulting from the extremely reduced output conductance and the increased transconductance in the GC devices are discussed, based on experimental results, establishing design guidelines in order to aim at GC micropower or wide bandwidth OTAs. Two-dimensional simulations are used to analyze the intrinsic-gate capacitances in the linear and saturation regions, establishing that GC transistors present almost the same capacitive load as the conventional fully-depleted transistors in a typical analog range of operation View full abstract»

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  • Low-voltage class AB operational amplifier

    Publication Year: 2001 , Page(s): 207 - 211
    Cited by:  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB) |  | HTML iconHTML  

    Presents a CMOS low-voltage operational amplifier, which uses a minimum selector circuit to control the class AB operation of the output stage. The operational amplifier basic characteristics are analyzed and simulated using the SMASH 4.0 simulator with the ACM model of the MOSFET. The supply voltage is 1.5V and the total quiescent current is 4.51 μA for a unity-gain frequency of 1 MHz. This design is being integrated on the AMS 0.8 μm CMOS technology. The operational amplifier presented here offers a competitive design choice for low-power low-voltage circuits View full abstract»

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  • On designing mixed-signal programmable fuzzy logic controllers as embedded subsystems in standard CMOS technologies

    Publication Year: 2001 , Page(s): 194 - 200
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB) |  | HTML iconHTML  

    A digitally-programmable analogue fuzzy logic controller (FLC) is presented. Input and output signals are processed in the analog domain whereas the parameters of the controller are stored in a built-in digital memory. Some new functional blocks have been designed whereas others were improved towards the optimisation of the power consumption, the speed and the modularity while keeping a reasonable accuracy, as it is needed in several analogue signal processing applications. A nine-rules, two-inputs and one-output prototype was fabricated and successfully tested using a standard CMOS 2.4μ technology, showing good agreement with the expected performances, namely: from 2.22 to 5.26 Mflips (mega fuzzy logic inferences per second) at the pin terminals (@CL= 13pF), 933 μW power consumption per rule (@Vdd=5V) and 5 bits of resolution. Since the circuit is intended for a subsystem embedded in an application chip (@CL⩽5pF) up to 8 Mflips may be expected View full abstract»

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  • A fast asynchronous re-configurable architecture for multimedia applications

    Publication Year: 2001 , Page(s): 150 - 155
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB) |  | HTML iconHTML  

    In this paper we describe a fast re-configurable asynchronous architecture for multimedia applications. The asynchronous architecture reflects the data-flow characteristics of such multimedia applications. As an example we realized the DCT/IDCT algorithms. These algorithms are used for MPEG encoding and decoding. The realized DCT/IDCT algorithms are based on those of Chen-Wang (1984). It is known as one of the most efficient implementations of the DCT/IDCT algorithms. Each DCT/IDCT consists of multiplications and additions. We realized one operator network of different asynchronous components to map the DCT and the IDCT on it. Furthermore, first simulation results of VHDL models show, the effectiveness of the approach View full abstract»

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  • RABBIT-a modular rapid-prototyping platform for distributed mechatronic systems

    Publication Year: 2001 , Page(s): 32 - 37
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB) |  | HTML iconHTML  

    A basic idea of the mechatronic design is to decompose a mechatronic system into subsystems in order to make the complex structure manageable. This paper introduces a platform, named RABBIT, which helps the designer in the development of mechatronic systems during the simulation and implementation stages. At these stages, software- and hardware-in-the-loop simulation is usually necessary. Our purpose is to develop a modular hardware and software platform for distributed real-time applications. The hardware comprises three main components: IEEE 1394, MPC555 microcontroller, and FPGA. The central aim of this project is high flexibility and extensibility of the platform. Two case-studies are described to exemplify the implementation of such a platform. One is named X-mobile (a novel modular mechatronic vehicle) and the other is the TESLA system (Test Site for Laboratory Automation) View full abstract»

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  • On a development environment for real-time information processing in system-on-chip solutions

    Publication Year: 2001 , Page(s): 28 - 31
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB) |  | HTML iconHTML  

    A design methodology for real-time information processing systems is presented An experimental platform offers the necessary computing power for speed intensive real-time algorithms as well as the necessary flexibility for control intensive software tasks. The fast prototyping experimental hardware platform represents a key step towards final system-on-chip (SoC) solutions by verifying the SoC implementation in the real-time environment and by analyzing the processed information data View full abstract»

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  • A Petri net based method for resource estimation: an approach considering data-dependency, causal and temporal precedences

    Publication Year: 2001 , Page(s): 78 - 84
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB) |  | HTML iconHTML  

    This work presents a combined reachability-structural methodology for computing the number of functional units in hardware/software co-design context considering timing constraints. The proposed method extends some previous works in the sense that data-dependency has been captured and considered in the functional unit estimation methodology. The proposed hardware/software co-design framework uses the Petri net as common formalism for performing quantitative and qualitative analysis View full abstract»

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