2016 IEEE 25th North Atlantic Test Workshop (NATW)

9-11 May 2016

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  • [Front cover]

    Publication Year: 2016, Page(s): C4
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  • [Title page i]

    Publication Year: 2016, Page(s): i
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  • [Title page iii]

    Publication Year: 2016, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2016, Page(s): iv
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  • Table of contents

    Publication Year: 2016, Page(s):v - vi
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  • Message from General and Program Chairs

    Publication Year: 2016, Page(s): vii
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  • Conference Organization

    Publication Year: 2016, Page(s): viii
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  • Program Committee

    Publication Year: 2016, Page(s): ix
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  • Steering Committee

    Publication Year: 2016, Page(s): x
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  • A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch Compensation Using Built-In Calibration

    Publication Year: 2016, Page(s):1 - 5
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    A 100MS/s 10-bit ADC design using a 130nm standard CMOS technology is presented in this paper. The proposed design adopted the split capacitor array digital-to-analog converter (DAC) to build successive approximation register (SAR) analog-to-digital converter (ADC) structure using a single input. On-chip mismatch calibration feature is utilized to compensate the capacitor mismatches of the DAC and... View full abstract»

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  • An Area Efficient 4Gb/s Half-Rate 3-Tap DFE with Current-Integrating Summer for Data Correction

    Publication Year: 2016, Page(s):6 - 11
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (556 KB) | HTML iconHTML

    This paper presents an area efficient 3-tap speculative Decision Feedback Equalizer (DFE) with a novel current-integrating summer for data self correction in standard CMOS 180nm technology node. The conventional first-tap speculative half-rate DFE is composed of four different paths, which have exactly same hardware. In this paper, a novel area efficient DFE is proposed where the four summers are ... View full abstract»

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  • Case Study of Testing a SoC Design with Mixed EDT Channel Sharing and Channel Broadcasting

    Publication Year: 2016, Page(s):12 - 17
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (290 KB) | HTML iconHTML

    Modern large SoC designs typically have many cores. Each core requires a certain number of input / output test channels. At the chip level, however, the total number of test channels is limited such that all core-level test channels cannot be accessed at the same time. One solution to this problem is obviously using hierarchical pattern retargeting, where cores can be wrapped and tested individual... View full abstract»

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  • Failures Guide Probabilistic Search for a Hard-to-Find Test

    Publication Year: 2016, Page(s):18 - 23
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (835 KB) | HTML iconHTML

    Previous research has firmly established the NPcomplete nature of the fault detection problem. Various algorithms and techniques have been developed to tackle the worst case computation time for test generation due to the increasing complexity of digital circuits. The development of these techniques over the past 50 years has improved a lot of commercial EDA tools. The efficiency of these tools co... View full abstract»

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  • Modeling Residual Life of an IC Considering Multiple Aging Mechanisms

    Publication Year: 2016, Page(s):24 - 27
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (180 KB) | HTML iconHTML

    Counterfeiting and recycling of integrated circuits (ICs) is a significant threat to the safety and security of commercial and military systems. To deter recycled ICs from entering the supply chain, the residual life of ICs should be metered. Several aging sensors have been proposed to track the semiconductor degradation effects, but there are very few works to monitor multiple aging mechanisms an... View full abstract»

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  • RAPIDO Testing and Modeling of Assisted Write and Read Operations for SRAMs

    Publication Year: 2016, Page(s):28 - 33
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (584 KB) | HTML iconHTML

    Lowering the supply voltage of Static Random-Access Memories (SRAM) is key to reduce an integrated circuit power consumption, however since this badly affects the circuit performances, it might lead to various failure modes of the memory circuit. While it is known that assist techniques can help in recovering functionality, it is hard to find a detailed model of those techniques. In this work, sta... View full abstract»

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  • Automated and Reusable IP Functional Test Rule Development across Multiple IP Instances within and across Asic Designs

    Publication Year: 2016, Page(s):34 - 37
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (295 KB) | HTML iconHTML

    Effective mixed-signal IP or core testing using an automated test methodology that is reusable across multiple IP instances, both within an ASIC and across various ASICs, is desirable for minimizing manufacturing test time, design changes for test, and maximizing yield while maintaining SPQL status. This paper presents an extended summary of two aspects of an illustrative approach to make function... View full abstract»

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  • A Tuning Technique for Temperature and Process Variation Compensation of Power Amplifiers with Digital Predistortion

    Publication Year: 2016, Page(s):38 - 45
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1667 KB) | HTML iconHTML

    Radio frequency (RF) power amplifiers (PAs) are the most power consuming and inefficient devices in RF transceiver systems and are often integrated with performance enhancement techniques such as digital predistortion (DPD). However, the performance of the integrated system (PA with DPD) is significantly impacted by temperature drift and process variations and thus it is essential to have a tuning... View full abstract»

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  • Using Existing Reconfigurable Logic in 3D Die Stacks for Test

    Publication Year: 2016, Page(s):46 - 52
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    We propose an architecture for an FPGA-based tester for a 3D stacked IC. Our design exploits the underlying structure of the FPGA, allowing it to be used to efficiently store and apply predefined test patterns at a high bandwidth, reducing the FPGA resources required and often reducing scan shift toggling. The proposed approach and its advantages can generally also be applied to 2.5D multi-die cir... View full abstract»

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  • Enabling Debug in IoT Wireless Development and Deployment with Security Considerations

    Publication Year: 2016, Page(s):53 - 58
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    This paper considers the debug needs of IoT devices and systems throughout their lifecycle, that also aims to preserve security required for IoT. A generic wireless debugging infrastructure over Bluetooth Low Energy (BLE) is proposed. We show how it is possible to balance the conflicting needs of security and visibility in a coherent framework based on leveraging an Android-powered device with pro... View full abstract»

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  • Author index

    Publication Year: 2016, Page(s): 59
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  • [Publisher's information]

    Publication Year: 2016, Page(s): 60
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