By Topic

Date 25-27 June 2001

Filter Results

Displaying Results 1 - 25 of 90
  • Device Research Conference. Conference Digest (Cat. No.01TH8561)

    Save to Project icon | Request Permissions | PDF file iconPDF (1124 KB)  
    Freely Available from IEEE
  • SOI and nanoscale MOSFETs

    Page(s): 3 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (258 KB) |  | HTML iconHTML  

    SOI may facilitate the fabrication of two attractive scalable MOSFET structures. Ultra-thin body FET has been demonstrated at 20 nm gate length, using low-barrier silicide S/D, with selectively deposited Ge raised S/D, on bulk substrate, or with Si-Ge channel. FinFET is a simple double gate FET with excellent performance and can be scaled to below 10 nm gate length-a candidate as the ultimate CMOS device. Adjusting the threshold voltage of a device with very thin body is challenging although several novel methods have been suggested. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Vertical cavity surface emitting laser-exploratory, emerging, or disruptive?

    Page(s): 5 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (242 KB) |  | HTML iconHTML  

    The vertical cavity surface emitting laser (VCSEL) is a relatively new class of semiconductor laser which can be monolithically fabricated. It is now considered as one of the important devices for Gigabit Ethernet, high speed LANs, computer links, optical interconnects, and so on. We review the technical progress of devices ranging from infrared to ultraviolet spectra by featuring physics, materials, fabrication technology, performances such as threshold, output powers, polarizations, modulation, tunability, reliability, and so on. Then, we discuss some emerging applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low-noise, high-speed avalanche photodiodes

    Page(s): 9 - 13
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (439 KB) |  | HTML iconHTML  

    Describes materials and structural modifications to the thin multiplication regions that have yielded ultra low multiplication noise. In the low gain regime, these APDs have achieved excess noise factors lower than that of Si APDs. Very high gain-bandwidth products can be achieved by proper design of the multiplication region and the use of a waveguide structure. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Status, prospects and commercialization of SiC power devices

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (86 KB)  

    Summary form only given. We have developed SiC Schottky diodes for blocking voltages ranging from 300 V to 1700 V covering a range of nominal currents from 4 A up to more than 25 A. Schottky diodes for blocking 300 V with nominal current ratings of 6 A and 10 A respectively, and for blocking 600 V with nominal current rating of 4 A and 6 A respectively, have already been commercialized by the parent Company Infineon Technologies AG; Schottky diodes for blocking 1200 V will follow soon. For higher blocking voltages up to 3 kV merged diodes were also successfully developed. We have also performed R&D on n-channel enhancement SiC MOSFETs. However, despite the promising performance ( 1800 V, 46 m/spl Omega/cm/sup 2/ e.g.) SiC MOSFET's are still far away from commercialization due to the lack of long term stability and an on-resistance sufficiently low enough to compete with their silicon enemies. As a rugged and very promising alternative to the SiC MOSFET we have developed vertical junction field effect transistors (VJFETs). View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-K gate dielectrics for sub-100 nm CMOS technology

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (82 KB) |  | HTML iconHTML  

    The materials and processing challenges for the fabrication of high quality, ultra-thin CVD high-K gate stack are reviewed along with the most recent results on CVD ZrO/sub 2/, HfO/sub 2/ and their silicates. The requirement for ultra thin and robust interface layers to avoid any thickness increase due to post-deposition processing to achieve thinnest equivalent oxide thickness (EOT) is discussed. Results are presented on thermal stability of high-K materials, and interfacial reactions of high-K/Si and highK/gate electrode. We also discuss key factors that govern the conduction and degradation mechanisms in high-K gate stack. Both poly-Si and poly-SiGe are explored as possible gate electrode materials and the upper thermal budget limit for such materials is discussed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fast write time and long retention 1T memory

    Page(s): 18 - 19
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (178 KB) |  | HTML iconHTML  

    It is desirable to achieve both fast data access time and long data retention time simultaneously. We have developed a 1T PZT/40 Å-Al/sub 2/O/sub 3/ memory to achieve very fast write (program/erase) time <100 ns, years long data retention, and good endurance >10/sup 10/ P/E cycles. The small 1T size is highly competitive with other memory technologies. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Physical origin of SILC and noisy breakdown in very thin silicon nitride gate dielectric

    Page(s): 20 - 21
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB) |  | HTML iconHTML  

    As the equivalent oxide thickness of the MOSFET gate dielectric continues to shrink, the transition to a material with a higher dielectric constant, such as Si/sub 3/N/sub 4/, seems imminent. It is well-recognized that stress-induced leakage current (SILC) and noisy (or soft) breakdown have become very important degradation phenomena in ultra-thin gate dielectrics. A lot of attention has been recently paid to SILC and soft breakdown in SiO/sub 2/ gate dielectrics, however the physical origins of these phenomena have not been thoroughly investigated. An understanding of the physical mechanisms responsible for the degradation of the ultra-thin gate dielectrics is critical to the development of a reliability model for the future generations of CMOS technology. This paper offers for the first time a detailed examination of SILC and noisy breakdown in Si/sub 3/N/sub 4/ demonstrating that these two degradation phenomena have a common origin. The nature of the traps responsible for SILC and noisy breakdown is revealed. The proposed degradation mechanism also provides a key to understanding and modeling of the dielectric reliability in the ultra-thin SiO/sub 2/ and new high-K gate materials. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low-power CMOS at Vdd = 4kT/q

    Page(s): 22 - 23
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (197 KB) |  | HTML iconHTML  

    Summary form only given. This paper reports a CMOS inverter active power-delay product of less than 0.1 fJ/stage at 25/spl deg/C and at Vdd=0.1 V. We believe this is the lowest reported. This is accomplished by using a novel technique to match NFET and PFET subthreshold currents and, thus, enable operation of a standard 1.5 V 180 nm CMOS technology in subthreshold at very low Vdd. This technique uses voltage feedback to the MOSFET wells to match the NFET off current (Ioffn) and PFET off current (Ioffp), significantly enhancing the manufacturability of CMOS subthreshold logic. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A sub 40-nm body thickness n-type FinFET

    Page(s): 24 - 25
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (206 KB) |  | HTML iconHTML  

    We experimentally demonstrate near-ideal subthreshold behavior of fully-depleted fin-style double-gate n-type MOSFETs and the best measured transconductance Gm-sat = 72 S/m (>400 S/m intrinsic) for sub-40 nm n-type FinFETs reported. This silicon nFET exhibits experimental ideality n = 1.13, in good agreement with the deviation from unity expected due only to source/drain coupling. These results comprise the best behavior for 100 nm-scale double-gate nFETs in terms of channel subthreshold characteristics and gate leakage observed experimentally to date. Hisamoto et al. (1989) introduced experimental results on doubld-gate silicon MOSFETs in which the channel is formed by etching single-crystal silicon to leave a vertical fin standing, forming a gate which wraps around the fin, with source and drain regions on the two ends of the fin. This basic idea was further refined to sub-50 nm n-type MOSFETs and then extended to sub-50 nm p-type MOSFETs. Using simplified fabrication techniques, we demonstrate improved behavior, from an intrinsic channel point of view, of the nFET work, using conventional CMOS integration on n-type FinFETs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Quasi-planar NMOS FinFETs with sub-100 nm gate lengths

    Page(s): 26 - 27
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (173 KB) |  | HTML iconHTML  

    Double-gate MOSFETs alleviate short channel effects and allow for more aggressive device scaling. Simulations have shown that scaling double-gated devices can reach 10 nm. In the past, process complexity has prevented serious development of a scalable double-gate device. In 1998, Hisarnoto et al. introduced a FinFET process that provided a method of fabricating devices with promising performance and scalability. Using a single poly layer across a silicon fin to form both gates in the double-gate structure, the FinFET benefits from having equally-sized, self-aligned gates. In this work, we have revamped the FinFET process flow to make it simpler. This improved process flow still has the self-aligned, double-gate advantage without suffering from extra gate-to-drain overlap capacitance. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High performance of planar double gate MOSFETs with thin backgate dielectrics

    Page(s): 28 - 29
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (223 KB) |  | HTML iconHTML  

    Planar double gate CMOS devices with thin silicon channels and electrically separate polysilicon top and bottom gates are fabricated. NFETs with L/sub design/=175 nm and 1.3 mA//spl mu/m and PFETs with L/sub design/=125 nm and 400 /spl mu/A//spl mu/m are achieved at V/sub dd/=1.2 V. To our knowledge, this is the largest current yet achieved in double gate NMOS devices. Electrical results show a high quality backgate dielectric, improvement of SCE using the backgate, and the importance of reducing external resistance in short channel devices. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Si/sub 1-x/Gex channel vertical PMOSFET with asymmetric Ge profile

    Page(s): 30 - 31
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (186 KB) |  | HTML iconHTML  

    Describes a vertical PMOSFET with an asymmetric Si/Si/sub 1-x/Ge/sub x/ channel . On the source side, the channel is made of Si, so the short channel performance is not degraded compared with a Si device. The rest of the channel is made of strained Si/sub 1-x/Ge/sub x/. and we still can take advantage of the high hole mobility in the strained Si/sub 1-x/Ge/sub x/ layer. The energy step in the channel increases the lateral electric field near the source and helps with carrier injection from the source to the channel. Ultra-high vacuum chemical vapor deposition (UHV-CVD) was used to grow the device layers with in situ doping. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optical interconnects to silicon CMOS

    Page(s): 35 - 38
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (321 KB) |  | HTML iconHTML  

    There are even greater problems for off-chip interconnects than on-chip ones. It is possible to break long on-chip interconnects up using on-chip repeater amplifiers, but that approach is very inconvenient off of the chip. Consequently, off-chip interconnects are a particularly attractive first implementation of optical interconnects to silicon chips. Optical interconnects are interesting for many reasons other than this scaling argument. They are immune to electromagnetic interference and crosstalk, they provide voltage isolation, they can have very low loss, and. they allow use of free-space optics, imaging many light beams from one chip to another. Historically a great impediment to integrating optical interconnects with CMOS was the absence of suitable optical output devices. Fortunately there are now two devices that may be able to fill this role - quantum-well modulator diodes, and vertical cavity surface emitting lasers (VCSELs). View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Temperature-dependent large signal modulation and Auger recombination in In/sub 0.4/Ga/sub 0.6/As quantum-dot lasers

    Page(s): 39 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB) |  | HTML iconHTML  

    Reports, to the best of the authors' knowledge, the first experimental determination of the Auger coefficients in quantum dots. In/sub 0.4/Ga/sub 0.6/As/GaAs self-organized quantum dot separate confinement heterostructure (SCH) lasers were grown by MBE. The active region consists of five coupled quantum dot layers. Single-mode ridge waveguide lasers with ridge widths 3/spl mu/m, 5/spl mu/m, and 8/spl mu/m and length 600/spl mu/m were fabricated by standard photolithographic techniques and cleaving of the facets. The peak lasing wavelength was measured to be 1.06/spl mu/m at room temperature, confirming lasing from ground state transitions. The lowest measured threshold current was 15 mA. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • ZnSe-based laser diodes for the 560 nm spectral region

    Page(s): 41 - 42
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (153 KB)  

    Reports the fabrication, the optimization and the operational characteristics of ZnSe-based laser diodes with quarternary ZnCdSSe quantum wells (QWs), specially designed to operate around 560 nm. The conventional double heterostructure, separate confinement design of the laser structures is realized with ZnMgSSe cladding and ZnSSe wave guiding layers. To obtain lasing emission at the desired spectral region high Cd contents are required for the QWs. The photoluminescence spectrum of such a laser diode. I indicates that these QWs can be grown at high optical quality despite the large lattice mismatch between the QW and the rest of the structure. The full width at half maximum of the QW emission is only 13 meV, which is close to the theoretical value for a mixed crystal with 45% Cd. High resolution X-ray diffraction measurements confirm the high crystal quality of the structure. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • NpN InGaAsN-based heterojunction bipolar transistors with f/sub max/ = 60 GHz

    Page(s): 43 - 44
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (161 KB)  

    Microwave measurements from 3x5 /spl mu/m/sup 2/ self-aligned NpN InGaAsN DHBT devices indicate that this low band gap material system can be successfully implemented in a GaAs-based HBT structure for lowering the turn-on voltage while attaining high-speed performance. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Noise characteristics of highly strained InGaP/InGaAs p-HEMTs grown on patterned substrates by using compound-source MBE

    Page(s): 45 - 46
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (165 KB) |  | HTML iconHTML  

    In this paper, we report on the low-frequency and microwave noise characteristics of the highly strained InGaP/In/sub 0.33/Ga/sub 0.67/As p-HEMTs grown on patterned substrate and the conventional InGaP/In/sub 0.22/Ga/sub 0.78/As p-HEMTs grown on non-patterned substrate. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A flip-flop based on monolithic integration of InAs/AlSb/GaSb RITDs and InAlAs/InGaAs/InP HEMTs

    Page(s): 47 - 48
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (178 KB) |  | HTML iconHTML  

    We report for the first time the demonstration of logic circuits based on the monolithic integration of high-speed submicron gate length InAlAs/InGaAs/InP HEMTs with InAs/AlSb/GaSb RITDs. An inverting D flip-flop was implemented using the MOBILE circuit architecture. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Monolithic integration of InAlAs/InGaAs enhancement and depletion (E/D)-mode metamorphic HEMTs on GaAs substrate

    Page(s): 49 - 50
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (209 KB) |  | HTML iconHTML  

    Except for a few studies on enhancement (E)-mode metamorphic HEMTs, most of the research studies so far however focused on depletion (D)-mode HEMTs. In view of excellent performance of D-mode devices, it is compelling to investigate E-mode devices as well. Moreover, once discrete devices are established, it becomes very much interesting to look into the monolithic integration of E- and D-mode devices as it finds an extensive application for ultra-high speed and low power digital circuits. To the best of our knowledge, there are no published results on monolithic integration of metamorphic E/D HEMTs so far. In this paper, we present results on monolithically integrated metamorphic In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As E/D HEMTs on GaAs substrate with gate-lengths down to 0.13 /spl mu/m. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Dual-channel SOI LIGBT with improved latch-up and forward voltage drop characteristics

    Page(s): 53 - 54
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (190 KB) |  | HTML iconHTML  

    To improve latch-up and forward voltage drop properties of the silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT), a new dual-channel structure is proposed and fabricated in this paper. The dual-channel structure is employed to enable more electrons to flow into the n-drift layer and improve the latch-up characteristic. This dual-channel SOI LIGBT results in significant improvement in latch-up current density. Simulated results indicate that the latch-up current density is improved by 4 times compared to that of the conventional SOI LIGBT. The dual-channel SOI LIGBT's were fabricated using a high voltage CMOS fabrication process. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Chaos generator MMIC's using resonant tunneling diodes

    Page(s): 55 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (151 KB) |  | HTML iconHTML  

    Recently, applications of chaos, which is often observed in nonlinear circuits, have been studied intensively in the field of information processing and communication systems. Using resonant tunneling devices to make such nonlinear circuits has many advantages, for example, simplicity in circuit, high operation frequency and low power consumption. In this paper, we report the demonstration of high-frequency operations of the chaos generator microwave monolithic ICs consisting of an RTD and a high electron mobility transistor (HEMT). View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High detectivity solar blind AlGaN metal-semiconductor-metal detector

    Page(s): 57 - 58
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (119 KB) |  | HTML iconHTML  

    Summary form only given. We have fabricated and characterized a solar blind detector based on AlGaN. The structure was grown on Si(111) by molecular beam epitaxy. After an AlN buffer, a GaN/AlN bilayer was grown, followed by a 1.6 /spl mu/m AlGaN layer, with about 50% Al. The process includes an optical lithography and PtAu Schottky contact deposition, and lift off. The cutoff wavelength is 280 nm, making this detector solar blind. The cut-off is very sharp, with 3 decades near UV rejection, limited by the contribution of the GaN layer. This performance represents the state of the art for solar blind MSM detectors based on AlGaN, and is very promising for applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Characterization of a 0.1 /spl mu/m MOSFET using cross-sectional scanning tunneling microscopy

    Page(s): 59 - 60
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (121 KB) |  | HTML iconHTML  

    A MOSFET structure was visualized in a nanometer scale using STM. Topographic STM images show the source/drain (S/D) regions, the poly-Si gate, and the very thin gate oxide layer on a nanometer scale. The results show that STM is a powerful technique to determine the depth of the S/D, the channel length, and the local carrier concentration. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Nanoscale MOSFETs scaling

    Page(s): 61 - 62
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (177 KB) |  | HTML iconHTML  

    We have carried out numerical modeling of room-temperature operation of Si dual-gate SOI MOSFETs with an ultra-thin, intrinsic (undoped) channel connecting bulk n/sup +/-doped source and drain. If the channel length L is of the order of 10 nm, electron-phonon and surface roughness scattering inside the channel may be neglected, and electron transfer is ballistic. Nevertheless, this transfer may still be well controlled by gate voltage, at small but practical thickness of gate oxide and channel. In contrast with the preliminary analytical model, in our present work the device electrostatics including band bending in source, drain and gate, has been treated explicitly using a numerical Poisson solver, and quantum-mechanical electron tunneling along the channel (under the maximum of the electrostatic potential created by the gate) has been taken into account self-consistently. The results show that the current saturation in very short MOSFETs is due to the transport bottleneck at the electron entrance into the channel, due to electron confinement both in energy and the spatial direction across the channel. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.