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On-Line Testing Workshop, 2001. Proceedings. Seventh International

Date 9-11 July 2001

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Displaying Results 1 - 25 of 39
  • Proceedings Seventh International On-Line Testing Workshop

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    Freely Available from IEEE
  • Author index

    Page(s): 227 - 228
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    Freely Available from IEEE
  • Using a WLFSR to embed test pattern pairs in minimum time

    Page(s): 75 - 79
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (404 KB) |  | HTML iconHTML  

    We propose a methodology for reducing the number of test cycles needed by a Weighted LFSR (WLFSR) to reproduce a 2P × W test matrix T of P pattern pairs. The methodology introduces a very small number of extra cells into the WLFSR and uses appropriate combinational mapping logic in order to make the time EP,W+δ·2 δ, where EP,W+δ is the time to generate vectors containing the W bits of the first pattern for each pair plus the δ extra bits. We present an algorithm that makes the value of δ less than or equal to [log2 λ], where λ is the size of the maximum subset of pairs in T with identical first patterns. This is a significant improvement over the time EP,W·P required by a trivial approach that uses a WLFSR with W cells to generate the first patterns of the pairs and a P × W ROM to store the second patterns of the pairs. Experimental results on the application of the methodology to the embedding of test matrices for path delay faults are particularly encouraging, even for very large numbers of test pattern pairs that are necessary for provably high fault coverage View full abstract»

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  • New reseeding technique for LFSR-based test pattern generation

    Page(s): 80 - 86
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    Presents a new reseeding technique for LFSR-based test pattern generation suitable for circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the LFSR jumps from a state to the required state (seed) by inverting the logic value of some of the bits of its next state. An efficient algorithm for selecting reseeding points is also presented, which targets complete fault coverage and minimization of the cardinality of the test set and the hardware required for the implementation of the test pattern generator. The application of the proposed technique to ISCAS '85 and the combinational part of ISCAS '89 benchmark circuits shows its superiority against the already known reseeding techniques with respect to the length of the test sequence and, in the majority of cases, the hardware required for their implementation View full abstract»

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  • Automatic bias generation using pipeline instruction state coverage for biased random instruction generation

    Page(s): 65 - 71
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (640 KB) |  | HTML iconHTML  

    Biased random instruction generators are commonly used in architectural verification of microprocessors, with biases specified manually by designers. As the complexity of processors grows, so does the complexity of specifying biases. Automatic bias generation speeds up the verification flow and may lead to better coverage of potential design errors. In this work, we present a deterministic algorithm to automatically generate biases that cover all pipeline states, where each pipeline state represents the positions and types of instructions in the pipeline. Test programs generated from these biases can be used for on-line testing in field applications. The quality of the biases generated is evaluated by using them to generate test programs and then simulating the test programs and evaluating various coverage metrics. Experimental results for the PowerPC and ARM7 architectures show that automatically generated biases result in higher design error coverage than random biases and provide better coverage of key architectural features View full abstract»

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  • On-line error detection techniques for dependable embedded processors with high complexity

    Page(s): 51 - 53
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB) |  | HTML iconHTML  

    Presents efficient techniques for concurrent error detection of processor components. It deals with concurrent check methods for complex data-path elements like FPUs or register-files. We propose a Berger code prediction unit for a multistage add-sub-FPU. Furthermore, the suitability of Berger code for register-files is discussed. As an alternative, the cross-parity observation is introduced. The applicability of these concepts was evaluated on several experimental processor designs up to double-precision pipeline processors View full abstract»

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  • Increasing the fault coverage in multiple clock domain systems by using on-line testing of synchronizers

    Page(s): 95 - 99
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (316 KB) |  | HTML iconHTML  

    As a result of shrinking minimum feature size, IC clock frequencies are increasing and it is no longer possible, nor desired, to stick to a single clock domain. Multiple-clock domain design will no longer be an isolated design style. This new trend in the industry, referred to as future standard by some companies, poses a lot of test problems due to special modules utilized at the interface between clock domains. These modules are called synchronizers. This paper will present an implementation of the on-line concept on two different synchronizers and it will calculate the probability to detect any stuck-at fault View full abstract»

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  • Fault tolerant automotive systems: an overview

    Page(s): 117 - 121
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (436 KB) |  | HTML iconHTML  

    There is a trend in the automobile industry for an increasing number of safety-related electronic systems in vehicles that are directly responsible for active and passive vehicle safety. These applications will increase overall vehicle safety by liberating the driver from routine tasks and assisting the driver to find solutions in critical situations. Thus it is of the utmost importance to solve fault tolerance issues of the electronic systems themselves. This paper gives an overview of the strategies and structures employed in the automotive environment to assure a good degree of fault tolerance both for complete systems and for integrated circuits View full abstract»

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  • Path-based error coverage prediction

    Page(s): 14 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (612 KB) |  | HTML iconHTML  

    Previous studies have shown that error detection coverage and other dependability measures estimated by fault injection experiments are affected by the workload. The workload is determined by the program executed during the experiments, and the input sequence to the program. In this paper, we present a promising analytical post-injection prediction technique, called path-based error coverage prediction, which reduces the effort of estimating error coverage for different input sequences. It predicts the error coverage for one input sequence based on fault injection results obtained for another input sequence. Although the accuracy of the prediction is low, path based error coverage prediction manages to correctly rank the input sequences with, respect to error detection coverage, provided that the difference in the actually coverage is significant. This technique may, drastically decrease the number of fault injection experiments, and thereby the time, needed to find the input sequence with the worst-case error coverage among a set of input sequences View full abstract»

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  • Effectiveness and limitations of various software techniques for "soft error" detection: a comparative study

    Page(s): 172 - 177
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    Deals with different software based strategies allowing the on-line detection of bit flip errors arising in microprocessor-based digital architectures as the consequence of the interaction with radiation. Fault injection experiments put in evidence the detection capabilities and the limitations of each of the studied techniques View full abstract»

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  • A gated clock scheme for low power scan-based BIST

    Page(s): 87 - 89
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    Presents a new low power scan-based BIST technique which can reduce the switching activity during test operation. The proposed low power/energy technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path View full abstract»

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  • Single output distributed two-rail checker with diagnosing capabilities for bus based self-checking architectures

    Page(s): 100 - 105
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (456 KB) |  | HTML iconHTML  

    This paper proposes a distributed two-rail checker (TRC) architecture which is specifically targeted to self-checking bus-based systems. The architecture makes use of a single bus line to provide error indication. With respect to conventional TRCs, additional diagnosing capabilities are provided. The checker is totally-self-checking with respect to stuck-at-faults. It features also good self-testing properties with respect to parametric faults, such as bridgings and delay-faults View full abstract»

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  • On the design of self-testing checkers for modified Berger codes

    Page(s): 153 - 157
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (376 KB) |  | HTML iconHTML  

    One of several approaches for designing highly-reliable systems relies on using error detecting codes (EDCs) and implementing digital circuits as self-checking. One class of EDCs that has been very often used to implement self-checking circuits are Berger codes. Although several self-testing checkers (STCs) for Berger codes have been proposed in the past, they mostly present area and delay results based on gate counts and gate levels and not on real implementations. In this work we consider real implementations and present and evaluate the area, delay and power characteristics of STCs for modified Berger codes that are based on: (a) parallel counters and (b) sorting networks. Preliminary results indicate that STCs based on parallel counters are smaller and consume less power than the STCs based on sorting networks View full abstract»

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  • Mixed-signal circuit classification in a pseudorandom testing scheme

    Page(s): 219 - 225
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB) |  | HTML iconHTML  

    Pseudorandom testing techniques for mixed-signal circuits offer several advantages compared to explicit time-domain and frequency-domain test methods. To fully exploit these advantages a suitable choice of the pseudorandom input parameters should be made and an investigation of the accuracy of the circuit response samples needed to reduce the risk of misclassification should be carried out. Here these issues have been addressed for a testing scheme based on the estimation of the impulse response of the device under test (DUT) by means of input-output cross-correlation. Moreover, new acceptance criteria for the DUT are suggested which solve some ambiguity problems arising if the classification of the DUT as good or bad is based on a few samples of the cross-correlation function. Examples of application of the proposed techniques to real cases are also shown in order to assess the impact of the measurement system inaccuracies on the reliability of the test View full abstract»

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  • Code-disjoint carry-dependent sum adder with partial look-ahead

    Page(s): 147 - 152
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    In this paper a self-checking code-disjoint carry-dependent sum adder is proposed. To reduce the hardware overhead, only every 4-th carry is generated by a look-ahead unit. To check the input parity, internal nodes of the adder cells are utilized View full abstract»

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  • Smart temperature sensor for on-line monitoring in automotive applications

    Page(s): 122 - 126
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB) |  | HTML iconHTML  

    This paper presents a system suitable for DfTT (Design for Thermal Testability) purposes that allows temperature monitoring and programmable overtemperature detection implemented in CMOS technology. It has been developed for on-line monitoring in automotive applications. The system includes a temperature sensor, based on the Base-emitter Voltage of a CMOS Lateral Bipolar Transistor, that achieves a non-linearity lower than 0,4°C in the range comprised between [-40°C, 85°C]. The system is compatible with the Boundary Scan protocol. The chip functions are discussed in detail View full abstract»

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  • Design and test of certifiable ASICs for safety-critical gas burner control

    Page(s): 197 - 201
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (460 KB) |  | HTML iconHTML  

    The purpose of this paper is to present a methodology and tools for the design and test of a EN298 compliant ASIC chip for safety-critical gas burner control, Safe operation, as far as the critical variable is concerned, is guaranteed in the presence of two simultaneous bridging or open defects. Emphasis is put on circumventing methodology, EDA (electronic design automation) and foundry limitations and on product certification requirements View full abstract»

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  • Testing FPGA delay faults in the system environment is very different from "ordinary" delay fault testing

    Page(s): 37 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (356 KB) |  | HTML iconHTML  

    Explains differences between testing delay faults in FPGAs and testing delay faults in circuits whose combinational sections can be represented as gate networks. Formulates - in a form suitable for analysis of LUT-based FPGAs - conditions that allow one to check whether or not a given input pair is a test of specific type (non-robust, robust, etc.). The presented theoretical results are shown to simplify an analysis of the various methods for enhancing the effectiveness of detection of FPGA delay faults View full abstract»

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  • DRAFT: an on-line fault detection method for dynamic and partially reconfigurable FPGAs

    Page(s): 34 - 36
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    Reconfigurable systems have benefited from the novel partial dynamic reconfiguration features of recent FPGA devices. Enabling the concurrent reconfiguration without disturbing system operation, this technology has raised a new test challenge: to assure a continuously fault free operation, independently of the circuit present after many reconfiguration processes, testing the FPGA without disturbing the whole system operation. Re-using the IEEE 1149.1 infrastructure, already widely used for In-System Programming, and exploiting the same dynamic and partially reconfigurable features underlying this test challenge, this paper develops a new structural concurrent test approach able to detect faults and introduce fault tolerance features, without disturbing system operation, in the field and throughout its lifetime View full abstract»

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  • Analyzing fault effects in fault insertion experiments

    Page(s): 21 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB) |  | HTML iconHTML  

    Addresses the problem of evaluating system sensitivity to hardware faults. For this purpose the authors use a software implemented fault injector with extended statistical capabilities (FITS). The main contribution of the paper is the formulation of basic factors influencing system dependability and checking them in experiments. These experiments have been performed on an IBM PC platform View full abstract»

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  • Test-per-clock testing of the circuits with scan

    Page(s): 90 - 92
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    The proposed test-per-clock testing scheme consists of an input scan chain, internal flip-flops, which are concatenated in the scan chain, auxiliary outputs for capturing the signals on the internal CUT outputs and a CUT test response compactor. The proposed method of finding the scan chain sequence uses the previously generated test patterns. The patterns have to contain a maximum number of don't care bits. For this reason we use non-compacted vectors; one vector corresponds to one fault. An algorithm for finding a sub minimal scan chain sequence was developed. The algorithm creates a scan chain sequence that forms on the scan chain flip-flops such vectors that exercise all considered faults of the circuit in a test-per-clock mode. Several experiments were done with ISCAS 85 and 89 benchmark circuits. Compared with the minimized compact test sets the proposed method substantially reduces the test application time, necessary hardware overhead and energy consumption View full abstract»

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  • Concurrent detection of soft errors based on current monitoring

    Page(s): 106 - 110
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB) |  | HTML iconHTML  

    Transient faults in future ICs turns to be a major consideration as the silicon process scales down. In this paper we propose a new soft error detecting technique with low area overhead, high detection speed and negligible performance penalty on the functional circuit under check. Among the already known techniques for soft error detection in logic circuits the proposed technique is the only one that is based on current monitoring View full abstract»

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  • Reliability properties assessment at system level: a co-design framework

    Page(s): 165 - 171
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (572 KB) |  | HTML iconHTML  

    The reliability co-design project aims at integrating in a standard hw/sw co-design flow the elements for achieving a final system able to detect the occurrence of a fault during its operational life. The paper presents the focus of the project, the definition and identification of design methodologies for implementing the nominal, checking and checker functionalities either in hardware or in software. An outline of the system specification and system partitioning aspects is also provided View full abstract»

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  • A new laser system for X-rays flashes sensitivity evaluation

    Page(s): 111 - 113
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB) |  | HTML iconHTML  

    This paper describes a new methodology using an optical laser bench for ICs X-rays-flashes sensitivity evaluation. Application to the study of one hardening technique of a BandGap Reference circuit is presented View full abstract»

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  • Fast configurable polynomial division for error control coding applications

    Page(s): 158 - 161
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB) |  | HTML iconHTML  

    The motivation for this paper is the need for high levels of reliability in modern telecommunication systems requiring very high data transmission rates. The search for technologically independent solutions, easy to implement on low cost and popular devices such as FPGA is an important issue. In this paper, we present a method to improve effectively the speed performance of the polynomial division performed in most error detecting and error correcting circuits. It is based on a pipeline structure for the polynomial division. Furthermore, the proposed solution is fully configurable, both from the static and the dynamic points of view. At synthesis stage, the parallelism level (size of the pipeline structure) and the maximal size of the polynomial divisor must both be chosen. Afterwards, the actual divisor can be chosen and changed while the circuit is running. The architecture proved to be very effective, as data rates up to 2.5 Gbits/s have been reached View full abstract»

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