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Bipolar Circuits and Technology Meeting, 1988., Proceedings of the 1988

Date 12-12 Sept. 1988

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Displaying Results 1 - 25 of 59
  • Proceedings of the 1988 Bipolar Circuits and Technology Meeting (Cat. No.88CH2592-4)

    Publication Year: 1988
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  • Switching characteristics of poly bipolar circuits at liquid nitrogen temperature

    Publication Year: 1988 , Page(s): 215 - 218
    Cited by:  Papers (6)
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    Measured data are presented on performance of current mode logic (CML) ring oscillators at liquid nitrogen temperature. The devices and circuits were fabricated using double-poly bipolar technology. The experimental data are explained using the hybrid-π model. CML ring oscillators were fabricated using 1.0 μm design rules. The measured delay at LN2 increased by a factor of 2.3 compared to that at room temperature. The increase in delay is explained by the temperature behavior of the base and load resistors View full abstract»

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  • A 3 GigaHertz 4:1 time division multiplexer with output retiming

    Publication Year: 1988 , Page(s): 146 - 149
    Cited by:  Papers (3)
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    A 3 GHz 4:1 multiplexer has been designed in Hewlett Packard's newest bipolar process. The circuit is fully differential and uses ECL-level outputs. Inputs are also ECL levels. The design uses a travelling wave divider approach to generate the timing signals for a 4:1 series gated asynchronous multiplexer. An output flip-flop and an inverting (on-chip) delay line are used in conjunction to retime the output data. The chip operates to 3 GHz from ~100 MHz with a power dissipation of 1.8 W. Off-chip drivers are on chip terminated to approximately 100 Ω to present a VSWR of better than 2:1 at the output. Full input registers lock in the data at the inputs View full abstract»

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  • Delay analysis for BiCMOS drivers

    Publication Year: 1988 , Page(s): 220 - 222
    Cited by:  Papers (17)
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    Simple delay models are derived for the different regions of operation for the bipolar transistors in a BiCMOS driver. The delay equations are approximate but extremely useful in relating the gate delay to the device and circuit parameters. Simulations from a mixed-level circuit and device simulator, CODECS, are used to verify the delay models. SPICE simulations are inadequate since high-level injection effects critical to the performance of the bipolar transistors are not well modeled with present bipolar transistor models in SPICE. The effects of various collector doping concentrations and epi-layer thickness are also investigated View full abstract»

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  • Measurement and modelling of the emitter resistance of polysilicon emitter transistors

    Publication Year: 1988 , Page(s): 55 - 58
    Cited by:  Papers (15)
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    A method for measuring the emitter resistance of polysilicon emitter transistors is described that separates the interface and metal/polysilicon contact components of the emitter resistance. Results show that for devices with a continuous interfacial layer the interface resistance controls the emitter resistance and is between 200 and 450 Ωμm2. This resistance is found to be current dependent and good agreement between theory and experiment is obtained. Results for devices with a discontinuous interfacial layer indicate that low interface resistances (17-33 Ωμm2) suitable for VLSI applications can be obtained by deliberately breaking up the interfacial layer. In this case the metal contact resistance contributes significantly to the total emitter resistance View full abstract»

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  • Scaling issues in the evolution of ExCL bipolar technology

    Publication Year: 1988 , Page(s): 121 - 124
    Cited by:  Papers (4)  |  Patents (1)
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    Several issues encountered in scaling ExCL technology are discussed. It is shown that doping profile scaling below 0.15 μm base width puts severe restrictions on process latitude. It is demonstrated that the polysilicon emitter resistance can be significantly reduced by rapid thermal annealing. Capacitance calculations show that interconnect-related parasitics do not scale below 3 μm pitch, and intralevel coupling may provide the ultimate limitation of interconnect scaling. Finally, the ExCL metallization scheme is proven to be scalable to 2 μm metal pitch View full abstract»

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  • Emitter resistance and performance trade-off of submicrometer self-aligned double-polysilicon bipolar devices

    Publication Year: 1988 , Page(s): 59 - 62
    Cited by:  Papers (1)
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    Emitter resistance dependences on emitter arsenic implant dose and diffusion temperature, emitter polysilicon film thickness and its two-dimensional effect, and in situ emitter surface cleaning with HCl gas for submicrometer self-aligned double-polysilicon bipolar transistors are described. Emitter resistance is also characterized as a function of emitter area ranging from 0.6×2.4 μm2 to 3.4×10.4 μm2. Cutoff frequency and ECL-gate delay time are compared between the devices with different emitter areas. Based on the experimental results and circuit simulations, and effects of device geometry scaling on emitter resistance and ECL circuit performance are discussed. It is predicted that an ECL-gate delay time of 35 psec with a cutoff frequency of 33 GHz can be expected at an operational current of 400 μA by achieving the emitter-base, base-collector, and collector-substrate capacitances of 3 fF, 2 fF, and 4 fF, respectively, with a neutral base width of 40 nm and an emitter resistance of 100 Ω View full abstract»

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  • A bipolar ECL static RAM with polysilicon diode loaded memory cell using single poly technology

    Publication Year: 1988 , Page(s): 28 - 31
    Cited by:  Papers (2)
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    A 1 K×1 bipolar emitter coupled logic (ECL) static random access memory (RAM) using a polysilicon diode loaded memory cell is realised in a single poly bipolar process technology. The use of the polysilicon diode as the load element for the memory cell is made possible by the fact that its I-V characteristics exhibit an ideality factor of two. The hold voltage for the memory cell is larger than 240 mV over a wide range of cell currents with the lower bound residing in the sub-μA range. Results show extremely stable operation against row select sensitivity. A 1.5-ns row address access time has been obtained from the test circuit View full abstract»

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  • GHz on-silicon-wafer probing calibration methods

    Publication Year: 1988 , Page(s): 154 - 157
    Cited by:  Papers (19)  |  Patents (37)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB)  

    Three calibration/correction techniques for on-silicon-wafer S-parameter measurements to 18 GHz were assessed by comparing calibration standards on sapphire and silicon. The effect of these techniques was evaluated by measuring large and small devices, connected to large and small pads. Equivalent circuit models for the calibration standards on silicon are presented. In addition, a new technique for on-wafer S-parameter measurements of backside collector devices is presented View full abstract»

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  • Avalanche multiplication in a compact bipolar transistor model for circuit simulation

    Publication Year: 1988 , Page(s): 103 - 106
    Cited by:  Papers (4)
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    Weak avalanche in bipolar transistors can be accurately modeled by using the collector depletion capacitance. This model has the advantages of a relatively fast numerical evaluation and an easily extracted avalanche parameter. The model incorporates internal voltage drop and temperature dependence and can be implemented in any compact bipolar transistor model View full abstract»

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  • CML III bipolar standard cell library

    Publication Year: 1988 , Page(s): 180 - 182
    Cited by:  Papers (1)  |  Patents (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    A 1.25 μm current mode logic (CML) bipolar standard cell library with subnanosecond loaded gate delays is discussed. Unique computer-aided design CAD tools that produce accurate models of the library cells and optimize designs for area, speed, and power are also discussed. The interplay between the library and the tools can produce higher speed, lower power chips, at less cost View full abstract»

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  • Effects of bandgap narrowing on the capacitance of silicon and GaAs pn junctions

    Publication Year: 1988 , Page(s): 195 - 198
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB)  

    The effect of heavy doping on the capacitance-voltage relation of abrupt and linearly-graded p-n junctions is studied by computer simulations. An estimate of bandgap narrowing in compensated silicon is given for linearly-graded junctions. Capacitance-voltage curves of abrupt p-n GaAs junctions grown by MBE are investigated and compared to the theoretical curves View full abstract»

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  • Characterization of polysilicon contacts by photoconductance measurements

    Publication Year: 1988 , Page(s): 125 - 127
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    The confinement property of polysilicon contacts, leading to storage of minority carriers, has been studied using the photoconductivity technique. Steady-state and transient optical measurement show a considerable increase of stored carriers by these contacts. A model has been developed that allows the extraction of contact parameters View full abstract»

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  • A precision dual `current feedback' operational amplifier

    Publication Year: 1988 , Page(s): 68 - 70
    Cited by:  Papers (15)
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    A high-speed monolithic dual operational amplifier using the `current feedback' approach is described which enables errors inherent in this type of amplifier to cancel in many applications. The advantages of this approach include a closed-loop bandwidth relatively independent of gain and a very high slew-rate capability. The disadvantages include considerably reduced DC performance compared to a conventional operational amplifier. Techniques for improving the DC performance of the individual amplifiers are described View full abstract»

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  • Comparing techniques for fabrication polysilicon contacted emitter bipolar transistors

    Publication Year: 1988 , Page(s): 63 - 66
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    Four methods for fabricating polysilicon-contacted BJTs have been investigated. In the first method polysilicon was deposited using low-pressure chemical vapor deposition (LPCVD) at 620°C. In the remaining three methods a-Si was first deposited and then recrystallized to form polysilicon. In the second method a-Si was deposited using LPCVD at 580°C. The third method used plasma-enhanced chemical vapor deposition (PECVD) to deposit a-Si-H. The fourth method involved a plasma etch with argon or hydrogen prior to deposition of a-Si:H using PECVD. The results indicated that using the PECVD method for depositing a-Si-H without any prior plasma-etch step and recrystallizing it to form polysilicon resulted in the highest current gain (β) enhancement of 3.5 and also allowed the reduction of the polysilicon anneal temperature down to 800°C or 900°C from 1000°C. The compactness in the spread of the peak β values for the devices fabricated using this technique also reflects its ability to reproducible fabrication of polysilicon contacted shallow emitter BJTs View full abstract»

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  • A multi-regional small-signal model derived from the charge-based large-signal bipolar transistor model

    Publication Year: 1988 , Page(s): 111 - 113
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (204 KB)  

    A multiregional small-signal model is derived from a charge-based large-signal bipolar transistor model, which has been upgraded to include emitter crowding, sidewall injection, and other multidimensional effects. This multiregional model is verified and the effect of this three-region analysis of the parameter extraction for the small-signal transistor model over a range of (low to high) injection conditions is demonstrated View full abstract»

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  • Package design for a microwave laser driver

    Publication Year: 1988 , Page(s): 158 - 161
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    A transmission line approach was employed in the design of the package for the laser driver. Two configurations were needed for routing the RF signal paths for the inputs and outputs. A modified microstrip, with ground shielding on both sides, was used to route the signal from the external lead to the central part of the package. A via, centered between two rows of ground vias, was used to route the signal path up to the chip level in the package. The results of electrical measurements performed on the four RF signal leads of the package are included. The measurements were made employing an HP-8510B network analyzer calibrated with a set of TRL fixtures. The results showed that the package would be good to 4.3 GHz for a return loss of -20 dB View full abstract»

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  • Modeling impact ionization in advanced bipolar transistors for device/circuit simulation

    Publication Year: 1988 , Page(s): 107 - 110
    Cited by:  Papers (4)
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    Impact ionization in advanced bipolar transistors, which depends on the complex electric-field distribution in the collector, is accounted for in a physical (seminumerical) device model. The collector analysis comprehensively treats quasi-saturation, and thus accounts for the formation of the current-induced space-charge region at high currents as well as the modulation of the junction space-charge region. Simulated (with MMSPICE) and measured characteristics are compared in support of the model View full abstract»

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  • A CMOS bipolar transistor with a locally doped base in the proximity of the emitter as a magnetic field sensor

    Publication Year: 1988 , Page(s): 199 - 201
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB)  

    A comparative study of a CMOS lateral magnetoresistor structure and a novel structure, with a locally doped base in the proximity of the emitter, is presented. For both structures a differential approach is used. The results indicate that the two locally doped p+-stripes restrict the injection of electrons from the emitter to the vertical direction, dramatically changing the path of the electrons flowing from the emitter laterally to the collectors. This in turn leads to a more effective deflection, by the magnetic field, of the electrons contributing to the collector current. As a result the magnetic sensitivity of the device is increased by more then three times View full abstract»

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  • A comparison of Si and Si1-xGex based BJTs using numerical simulation

    Publication Year: 1988 , Page(s): 46 - 48
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    Static and small signal performances of Si and Si1-xGe x based bipolar junction transistors (BJTs) are compared using numerical simulation. Si1-xGex BJT shows reduced turn-on voltage (ΔVBE=0.12 V), much higher current gain hfe, up to two time higher unity current gain frequency fT, and somewhat higher maximum frequency of oscillation fmax. By using Si 1-xGex it is possible to reduce power dissipation in the circuit environment. Small signal current gain, as obtained by using the quasi-static approximation, is shown for the common emitter configuration View full abstract»

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  • High frequency characterization of small geometry bipolar transistors

    Publication Year: 1988 , Page(s): 91 - 94
    Cited by:  Papers (4)
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    Small-signal high-frequency measurements of small bipolar transistors, carried out `on wafer' up to a frequency of 18 GHz, are presented. Current gain, transconductance, and maximum power gain characteristics as a function of frequency and DC bias conditions have been obtained with accurate calibration and correction techniques. The figures of merit, ftfy, and fmax, associated with these characteristics have been discussed, and a simplified analysis of the relevant time constants has been given. Simulation results with a modified Gummel/Poon model show that good high-frequency modeling can be achieved by taking into account the current dependence of the base resistance and the base transit time, and the modeling of excess phase shift. Finally the importance of modeling the distributed base-collector capacitance, which is accomplished in the Gummel/Poon model with the parameter x cjc, has been emphasized. It is very important even for frequencies well below the cutoff frequency View full abstract»

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  • The effect of emitter sidewall isolation on the emitter junction in a double layer polysilicon bipolar process

    Publication Year: 1988 , Page(s): 128 - 131
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    The 2D equi-concentration dopant contours are revealed for the first time for a cross-section through a 1 μm double-layer polysilicon bipolar device. The planarity of the emitter junction is shown to be dependent on the presence of emitter sidewall spacer filters. Implications for ultrashallow junction devices are presented View full abstract»

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  • A versatile monolithic RF amplifier using a dielectrically isolated monolithic microwave integrated circuit (DIMMIC)

    Publication Year: 1988 , Page(s): d137 - d140
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    A new RF integrated-circuit technology is described that overcomes the drawbacks of currently available integrated processes. This DIMMIC technology draws its advantage from its dielectric isolation, which minimizes parasitic substrate capacitance, and from its lack of increased collector resistance. Using this technology, a medium-power RF amplifier was built that reduced parts count and size significantly over its discrete counterpart without sacrificing performance View full abstract»

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  • Heteroface bipolar transistor based on bandgap narrowing in p+ -GaAs

    Publication Year: 1988 , Page(s): 33 - 36
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    A n-p-n bipolar transistor that will be comparable in performance to conventional heterostructure bipolar transistors, but will be far easier to manufacture, is described. The device features an n-GaAs:p+-GaAs emitter-base junction and makes use of bandgap shrinkage in the p+-GaAs to maintain high emitter injection efficiency. Measurements of bandgap shrinkage in p+-GaAs are reviewed. The DC performance of the new device, in terms of the current gain, is expected to be excellent View full abstract»

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  • Thin base formation by double diffused polysilicon technology

    Publication Year: 1988 , Page(s): 132 - 135
    Cited by:  Papers (7)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    The method of double-diffused emitter-base formation is characterized. It is shown to be a viable technique for the fabrication of advanced bipolar transistors. The use of amorphous instead of polycrystalline silicon as the emitter contact material results in a shallower emitter-base junction and little effect of the boron diffusion on the obtained arsenic profile. The narrowing of the base yields a higher intrinsic base resistance for the same number of carriers leading to a decrease in current gain for the same intrinsic base resistance. The different processing of double diffusion compared to base implantation may also lead to a loss in emitter efficiency. Nevertheless uniformity of the basewidth seems to be excellent and good high-frequency characteristics (up to fT=15 GHz) are obtained View full abstract»

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