By Topic

2015 10th International Design & Test Symposium (IDT)

14-16 Dec. 2015

Filter Results

Displaying Results 1 - 25 of 40
  • [Front cover]

    Publication Year: 2015, Page(s): c1
    Request permission for commercial reuse | PDF file iconPDF (419 KB)
    Freely Available from IEEE
  • [Copyright notice]

    Publication Year: 2015, Page(s): 1
    Request permission for commercial reuse | PDF file iconPDF (172 KB)
    Freely Available from IEEE
  • Organizing Committee

    Publication Year: 2015, Page(s):ii - iv
    Request permission for commercial reuse | PDF file iconPDF (100 KB)
    Freely Available from IEEE
  • Technical program committee

    Publication Year: 2015, Page(s): v
    Request permission for commercial reuse | PDF file iconPDF (87 KB)
    Freely Available from IEEE
  • Chairs' message

    Publication Year: 2015, Page(s): ix
    Request permission for commercial reuse | PDF file iconPDF (81 KB) | HTML iconHTML
    Freely Available from IEEE
  • Keynote 1: "Merger mania"

    Publication Year: 2015, Page(s): 1
    Request permission for commercial reuse | PDF file iconPDF (80 KB) | HTML iconHTML
    Freely Available from IEEE
  • Keynote 2: "Computing for big-data: Beyond CMOS and beyond Von-Neumann"

    Publication Year: 2015, Page(s): 1
    Request permission for commercial reuse | PDF file iconPDF (126 KB) | HTML iconHTML
    Freely Available from IEEE
  • Keynote 3: "Ensuring robustness in today's IoT era"

    Publication Year: 2015, Page(s): 1
    Cited by:  Papers (2)
    Request permission for commercial reuse | PDF file iconPDF (111 KB) | HTML iconHTML
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2015, Page(s):vi - viii
    Request permission for commercial reuse | PDF file iconPDF (122 KB)
    Freely Available from IEEE
  • Transforming between logic locking and IC camouflaging

    Publication Year: 2015, Page(s):1 - 4
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB) | HTML iconHTML

    The globalization of IC design has resulted in security vulnerabilities and trust issues such as piracy, overbuilding, reverse engineering and Hardware Trojans. Logic locking and IC camouflaging are two techniques that help thwart piracy and reverse engineering attacks by making modifications at the netlist level and the layout level, respectively. In this paper, we analyze the similarities and di... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Obfuscated arbitrary computation using cryptographic primitives

    Publication Year: 2015, Page(s):5 - 8
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (122 KB) | HTML iconHTML

    The breakthrough of fully homomorphic encryption (FHE) enables privacy-preserving arbitrary computation in the cloud, supporting both addition and multiplication over encrypted data. Current FHE implementations, however, suffer from high performance overheads and require expensive boot-strapping operations to decrease ciphertext noise. In this work, we discuss how homomorphic encryption primitives... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reliability degradation in the scope of aging ??? From physical to system level

    Publication Year: 2015, Page(s):9 - 12
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB) | HTML iconHTML

    Advances in technology have paved the way for making embedded on-chip systems ubiquitous in our daily life. Unfortunately, compared to previous generations, the current nano-CMOS era introduces reliability challenges at an increased pace. As a matter of fact, technology scaling is reaching its limits where certain aspects endanger the correct functionality of hardware/software on-chip systems. The... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Revolutionizing validation: The Intel approach for TTM

    Publication Year: 2015, Page(s): 13
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB) | HTML iconHTML

    Summary form only given. Intel is focused on gaining a foothold in the burgeoning mobile/IOT computing market. One of the unique challenges in this dynamic market is the aggressive time-to-market (TTM) requirement. In the past, the length of the silicon validation stage for Intel SoCs contributed to the company's inability to deliver products on time, taking up to two years for prior projects. To ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • SoC verification platforms using HW emulation and co-modeling Testbench technologies

    Publication Year: 2015, Page(s):14 - 19
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1290 KB) | HTML iconHTML

    Hardware-assisted verification, or emulation, delivers the capacity and performance for extremely fast, full System-on-Chip (SoC) testing. Emulation enables longer test cases and more tests to be run in less time. In doing so, it allows more design requirements to be covered while more bugs are uncovered. However, emulation is no longer only about performance and capacity. The landscape is shiftin... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Chip-level programming of heterogeneous multiprocessors

    Publication Year: 2015, Page(s):20 - 25
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (327 KB) | HTML iconHTML

    Chip Heterogeneous Multiprocessors (CHMs) are increasingly emerging as a means to optimize energy and performance over a wide spectrum of application programs. However, unlike traditional processors no programming model has been developed for CHMs. This paper proposes a set of programming primitives and benchmarking strategies for CHMs. We demonstrate our proposal by showing how architects can eva... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Heterogeneous multi-core architecture for a 4G communication in high-speed railway

    Publication Year: 2015, Page(s):26 - 31
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (543 KB) | HTML iconHTML

    The fast development of high-speed railway (HSR), as a high-mobility intelligent transportation system (ITS), and the growing demand of broadband services for HSR users, introduce new challenges to wireless communication systems. 4G Long Term Evolution (LTE) standard has been widely used to satisfy the HSR communication system needs. The key part of 4G LTE standard is the Orthogonal Frequency Divi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Memory profiling for intra-application data-communication quantification: A survey

    Publication Year: 2015, Page(s):32 - 37
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (153 KB) | HTML iconHTML

    With the advent of technology, multi-core architectures are prevalent in embedded, general-purpose as well as high-performance computing. Efficient utilization of these platforms in an architecture agnostic way is an extremely challenging task. Hence, profiling tools are essential for programmers to optimize the applications for these architectures and understand the bottlenecks. Typical bottlenec... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 10 Gbps ADC-based equalizer for serial I/O receiver

    Publication Year: 2015, Page(s):38 - 43
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (758 KB) | HTML iconHTML

    This paper introduces the system architecture and implementation of a 10Gbps ADC-Based Equalizer for Serial I/O Receiver. The system consists of 2 main building blocks. The first is a 4-channel 4-bit flash analog-to-digital converter with 10 Gbps sampling speed which was implemented using a modified clocking scheme that improves the ADC accuracy and resolution without the need for digital calibrat... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low-temperature-coefficient curvature-compensated bandgap reference with mismatch attenuation

    Publication Year: 2015, Page(s):44 - 48
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB) | HTML iconHTML

    A high-order curvature-compensated bandgap reference (BGR) with low temperature coefficient (TC) is proposed in this paper. The curvature compensation is maintained through the use of Pplus poly resistor and Nplus poly resistor to achieve temperature-dependent resistor ratios. A T-resistor structure is adopted which enables the BGR to work under low supply voltage or high MOSFET threshold voltage ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Toward the interfacing of systemC-AMS models with hardware-emulated platforms

    Publication Year: 2015, Page(s):54 - 59
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (226 KB) | HTML iconHTML

    Systems on chip (SoC) nowadays, have become heterogeneous in nature. They can be composed of a mix of analog and digital components. In some verification environments, SystemC models the digital components and SystemC-AMS extensions can be used to model the analog part. In an emulation environment, the digital components would be probably running on the emulator while the SystemC-AMS components wo... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Guiding intelligent testbench automation using data mining and formal methods

    Publication Year: 2015, Page(s):60 - 65
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (710 KB) | HTML iconHTML

    Achieving coverage closure is consistently identified as one of the most difficult challenges during the functional verification of today's HW designs. Constraint random testing as well as coverage directed test generation (CDTG) techniques have been proposed previously with different degree of success. This paper presents a framework for speeding up the coverage closure of the design under verifi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multiple fault testing in systems-on-chip with high-level decision diagrams

    Publication Year: 2015, Page(s):66 - 71
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (373 KB) | HTML iconHTML

    A new method of high level test generation based on the concept of test groups to prove the correctness of a part of system functionality is proposed. High-level faults of any multiplicity are assumed to be present in the system, however, there will be no need to enumerate them. Unlike the known approaches, we do not target the faults as test objectives. The goal of using the test groups is to ext... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reconfigurable test platform for modular embedded systems in manufacturing processes

    Publication Year: 2015, Page(s):72 - 77
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (629 KB) | HTML iconHTML

    This paper presents a platform developed for in production testing of modular embedded systems. These systems are flexible and low cost, with respect to production and maintenance. However, they require a complex testing process, in order to reduce the flaws in the production process and increase the rate of certified modules. For the manufacturers, modular embedded systems offer the possibility o... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An automatic ECG generator for testing and evaluating ECG sensor algorithms

    Publication Year: 2015, Page(s):78 - 83
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (507 KB) | HTML iconHTML

    The use of biomedical sensors, be it attached or embedded inside a human body, to monitor various physiological parameters is increasing at a significant rate due to continued advances in miniaturizations and materials. Testing and verification of the algorithms used in processing the physiological parameters of concern is essential, given the sensitivity of their usage. Simulation is a technique ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient data management on 3D stacked memory for big data applications

    Publication Year: 2015, Page(s):84 - 89
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB) | HTML iconHTML

    Big data processing has been an increasingly important field which has attracted a lot of attention from academia and industry. However, it worsens the memory wall problem for processor design, which means a large performance gap between processor computation and memory access. The 3D stacked memory structure has been put forward as a promising method to relieve this problem. As non-volatile memor... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.