Multiple-Valued Logic, 2001. Proceedings. 31st IEEE International Symposium on
Date 22-24 May 2001
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Displaying Results 1 - 25 of 53
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Proceedings 31st IEEE International Symposium on Multiple-Valued Logic
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PDF (261 KB)
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Author index
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PDF (88 KB)
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A three-valued D-flip-flop and shift register using multiple-junction surface tunnel transistors
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PDF (308 KB)
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A model of reaction-diffusion cellular automata for massively parallel molecular computing
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PDF (520 KB)
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Compact SOP representations for multiple-output functions-an encoding method using multiple-valued logic
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PDF (368 KB)
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A 4 digit CMOS quaternary to analog converter with current switch and neuron MOS down-literal circuit
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PDF (352 KB)
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Many valued paraconsistent logic
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PDF (504 KB)
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Polynomial-time algorithms for verification of some properties of k-valued functions represented by polynomials
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PDF (420 KB)
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Spectral techniques in binary and multiple-valued switching theory. A review of results in the decade 1991-2000
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PDF (488 KB)
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An application of multiple-valued logic to test case generation for software system functional testing
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PDF (356 KB)
