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2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167)

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• 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167)

Publication Year: 2001
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• Biographies

Publication Year: 2001, Page(s):431 - 451
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• Comparison of via/line package level vs. wafer level results

Publication Year: 2001, Page(s):194 - 199
Cited by:  Papers (9)  |  Patents (1)
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Comparison of lifetime projections from a wafer level test and a package level test (on equivalent parts) is demonstrated, given activation energy and current density exponent from the package level test. Comparison of the acceleration factor between the wafer and package level tests yields good agreement and is described in detail. Kinetics determined from both tests are presented. Physical failu... View full abstract»

• Experimental comparison of wafer level reliability (WLR) and packaged electromigration tests

Publication Year: 2001, Page(s):189 - 193
Cited by:  Papers (5)
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The wafer level reliability (WLR) electromigration (EM) test is a quick test under very highly accelerated conditions using a parametric tester and prober on a full-sized wafer, which can provide cost effective and timely feedback on possible reliability degradation due to process variation/modification, equipment change, or misprocessing (Pierce and Snyder, 1997; McPherson, 1996). Under these hig... View full abstract»

• Advanced 2D latch-up device simulation-a powerful tool during development in the pre-silicon phase

Publication Year: 2001, Page(s):235 - 239
Cited by:  Papers (4)
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The consideration of parasitic effects like the ESD and latch-up sensitivity of a new technology in the early development phase is not yet established. Calibrated 2D simulation can be used for optimizing the technology according to these parasitic effects yielding to an area optimized protection concept and thus offering the possibility to reduce chip costs. In this paper, we present a 2D latch-up... View full abstract»

• Real case study for isothermal EM test as a process control methodology

Publication Year: 2001, Page(s):184 - 188
Cited by:  Papers (3)
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The isothermal electromigration (EM) test is a very quick method to evaluate metal quality (Jones and Smith, 1987). However, most people do not have adequate confidence in its accuracy due to the fact that its failure mechanism is not easily controlled. By carefully controlling the failure criteria, we have shown that the failure mechanism in isothermal is similar to that of conventional EM tests.... View full abstract»

• Non-uniform bipolar conduction in single finger NMOS transistors and implications for deep submicron ESD design

Publication Year: 2001, Page(s):226 - 234
Cited by:  Papers (7)  |  Patents (6)
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This paper presents a detailed study of the nonuniform bipolar conduction phenomenon in single finger NMOS transistors and analyses its implications for deep submicron ESD design. It is shown that the uniformity of lateral bipolar triggering is severely degraded with device width (W) in advanced technologies with silicided diffusions and low resistance substrates, and that this effect can only be ... View full abstract»

• Comparison of isothermal, constant current and SWEAT wafer level EM testing methods

Publication Year: 2001, Page(s):172 - 183
Cited by:  Papers (6)  |  Patents (1)
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We present data from three wafer level electromigration test techniques, isothermal (ISOT), constant current (CI), and standard wafer level electromigration accelerated test (SWEAT) and compare various aspects of the data. ISOT keeps the test line at a constant temperature. CI applies a constant current of the same magnitude to all lines, without making any adjustments for individual geometric dif... View full abstract»

• Improvement in retention reliability of SONOS nonvolatile memory devices by two-step high temperature deuterium anneals

Publication Year: 2001, Page(s):52 - 56
Cited by:  Papers (1)  |  Patents (1)
| | PDF (320 KB) | HTML

The deterioration of the Si-SiO2 interface is associated with the degradation of long term retention in polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memory (NVSM) devices. Two-step high temperature deuterium anneals, applied in SONOS device fabrication for the first time, improve the endurance characteristics and retention reliability over traditional hydrog... View full abstract»

• Analysis of new hot carrier degradation phenomena: W' or S' shape evolution of LDD NMOSFET

Publication Year: 2001, Page(s):406 - 411
Cited by:  Papers (3)
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A new phenomenon has been observed for transistors with super steep channel retrograde well (SSRW) channel and lightly doped drain (LDD) structure. This is the `W' or “S” shape evolution of drain current and transconductance (Gm) during hot carrier stress. This “S” shape evolution does not follow the conventional power law degradation model A·tn... View full abstract»

• Characterization and investigation of the interaction between hot electron and electrostatic discharge stresses using NMOS devices in 0.13 μm CMOS technology

Publication Year: 2001, Page(s):219 - 225
Cited by:  Papers (6)
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In this paper, the high-current characteristics encountered during electrostatic discharge (ESD) events using NMOS/Lnpn protection devices in a 0.13 μm CMOS technology are investigated for different device parameters. The effects of silicide blocking and hot electron (HE) shifts on the second breakdown current of the NMOS devices are studied. The impact of nondestructive ESD stressing on HE shi... View full abstract»

• Calculating the error in long term oxide reliability estimates

Publication Year: 2001, Page(s):168 - 171
Cited by:  Papers (7)
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Ultra-thin oxide reliability is a critical issue in integrated circuit scaling. Oxide reliability may actually prevent future scaling of SiO2 gate dielectrics. The statistical error in long term oxide reliability projections has not been cohesively treated. Using Monte Carlo techniques, the amount of uncertainty in reliability projections is calculated. Applying the derived results to t... View full abstract»

• The concept of relative damage stress and its application to electronic packaging solder joint reliability

Publication Year: 2001, Page(s):128 - 131
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A new mechanical concept, relative damage stress, which can mechanically reflect the failure mechanism of solder joints used in electronic packaging in full-scale, has been proposed. Based upon the new mechanical concept, the thermal fatigue life data of surface mount solder joints have been reasonably analyzed, something that traditional mechanical concepts, such as Mises equivalent stress, can n... View full abstract»

• The effects of STI process parameters on the integrity of dual gate oxides

Publication Year: 2001, Page(s):48 - 51
Cited by:  Papers (2)  |  Patents (4)
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The reliability of dual gate oxide has been investigated in terms of dual gate oxide and shallow trench isolation (STI) process parameters. The thick oxide constructed by the dual gate oxide process shows intrinsic inferior quality to single-step grown thin oxide due to differences in its fabrication process, mainly the double-growth scheme. A larger susceptibility to STI process parameters is als... View full abstract»

• Role of e-e scattering in the enhancement of channel hot carrier degradation of deep sub-micron NMOSFETs at high VGS conditions

Publication Year: 2001, Page(s):399 - 405
Cited by:  Papers (2)
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It has been reported in the literature (Rauch et al., 1998; Wang-Ratkovic et al., 1997; Su et al, 1996; Li et al., 1999) that in deep submicron NMOSFETs the worst channel hot carrier (CHC) degradation is not near the peak substrate current (as predicted by the lucky electron model (Hu et al., 1985)), but at the VGS=VDS bias condition. We propose a new CHC model based on an e... View full abstract»

• Degradation characteristics of AlGaN-GaN high electron mobility transistors

Publication Year: 2001, Page(s):214 - 218
Cited by:  Papers (10)  |  Patents (1)
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AlGaN-GaN high electron mobility transistors (HEMTs) have shown great potential for high temperature/high power electronics. However, the study on the reliability of GaN-based devices is still at the initial stages. In this work, we report the degradation characteristics of AlGaN HEMTs under various stress conditions such as DC stress (gate current extraction and hot electron cycles) and RF input ... View full abstract»

• N-channel versus p-channel flash EEPROM-which one has better reliabilities

Publication Year: 2001, Page(s):67 - 72
Cited by:  Papers (3)  |  Patents (11)
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In this paper, a comprehensive study of n- and p-channel flash cells in terms of performance and reliability is presented. In particular, hot-carrier reliability issues such as disturbs and endurance in both n- and p-channel flash cells are also investigated. The most serious reliability issue in p-channel flash memory, drain disturb, can be overcome by using a DINOR structure. These results can b... View full abstract»

• Full three-dimensional motion characterization of a gimballed electrostatic microactuator

Publication Year: 2001, Page(s):91 - 98
Cited by:  Papers (2)
| | PDF (780 KB) | HTML

Advanced testing methods for the dynamics of microdevices are necessary to develop reliable marketable microelectromechanical systems (MEMS). The main purpose for MEMS testing is to provide feedback to the design-and-simulation process in an engineering development effort. This feedback should include device behavior, system parameters, and material properties. An essential part of more effective ... View full abstract»

• Trade-off between reliability and post-CMP defects during recrystallization anneal for copper damascene interconnects

Publication Year: 2001, Page(s):350 - 354
Cited by:  Papers (6)  |  Patents (8)
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Thermal treatments of electroplated copper films before CMP can increase grain size and therefore reduce resistance and improve electromigration reliability. However, high temperature excursions can also increase the stress levels in thick metal layers due to differential thermal expansion, which in turn can increase the occurrence of post-CMP defects such as pullouts and line voids. In this paper... View full abstract»

• Reservoir modeling for electromigration improvement of metal systems with refractory barriers

Publication Year: 2001, Page(s):327 - 333
Cited by:  Papers (2)  |  Patents (44)
| | PDF (756 KB) | HTML

Metal ion reservoirs in a Ti-AlCu-TiN metal system with W vias have been shown to increase electromigration lifetimes in barrier metal systems. In this study, it is empirically shown that EM lifetime increase is related to the natural-log of reservoir length in a constant width line. In this process, where vias do not penetrate the barrier, the number of vias, via spacing, and metal overlap do not... View full abstract»

• Softening of breakdown in ultra-thin gate oxide nMOSFETs at low inversion layer density

Publication Year: 2001, Page(s):163 - 167
Cited by:  Papers (8)  |  Patents (30)
| | PDF (336 KB) | HTML

The post breakdown I-V characteristics of ultra-thin gate oxides subjected to constant voltage Fowler-Nordheim stress in nMOSFETs were investigated. It is shown that by varying the electron density through the application of a substrate bias under the same stress field conditions, the oxide degradation does not change while the oxide I-V characteristics after the breakdown event are strongly modif... View full abstract»

• A fatigue theory for solders

Publication Year: 2001, Page(s):120 - 127
Cited by:  Papers (1)
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A fatigue theory with its definition of fatigue failure criterion based on physical damage mechanisms is presented for solders. The theory applies Mura's micromechanical fatigue model to each individual grain of the solder structure, where grain's crystallographic orientation is taken into account. A solder structure is defined as fatigued when the ratio of its failed grains reaches a critical per... View full abstract»

• A study of formation and failure mechanism of CMP scratch induced defects on ILD in a W-damascene interconnect SRAM cell

Publication Year: 2001, Page(s):42 - 47
Cited by:  Papers (4)  |  Patents (1)
| | PDF (532 KB) | HTML

In this study, we investigated the reliability failure mechanism of CMP induced defects in SRAM. A high temperature operating life (HTOL) accelerated test was performed to examine the long-term reliability. It was found that the CMP scratches could cause not only an initial failure but also a fatal long-term reliability failure. The failure mechanism is similar to time dependent dielectric breakdo... View full abstract»

• Soft breakdown triggers for large area capacitors under constant voltage stress

Publication Year: 2001, Page(s):393 - 398
Cited by:  Papers (3)
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This work quantitatively compares breakdown triggers for constant voltage stress of large area NMOS capacitors (up to 10 mm2) with 1.8 to 12 nm gate oxide thickness (with negative VG). We conclude that in the studied range, breakdown is identified more reliably with a current step trigger than through increased current fluctuation (RMS). We also present data filtering algorit... View full abstract»

• Low-temperature, high-current lifetests on InP-based HBT's

Publication Year: 2001, Page(s):206 - 213
Cited by:  Papers (5)
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Accelerated lifetests have been conducted on AlInAs-GaInAs HBT devices on InP wafers. Current densities were relatively high, while junction temperatures were low enough (125 and 160°C) to provide a check for low activation energy failures. 40 devices were tested, and about 14,000 hours have been accumulated so far. Changes similar to those found in conventional higher-temperature lifetests we... View full abstract»