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ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

6-9 May 2001

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  • Reviewers

    Publication Year: 2001, Page(s):ix - xix
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  • The 2001 IEEE International Symposium on Circuits and Systems

    Publication Year: 2001, Page(s):0_2 - lxxii
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  • A combined tree growing technique for block-test scheduling under power constraints

    Publication Year: 2001, Page(s):255 - 258 vol. 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB) | HTML iconHTML

    A tree growing technique is used here together with classical scheduling algorithms in order to improve the test concurrency having assigned power dissipation limits. First of all, the problem of unequal-length block-test scheduling under power dissipation constraints is modeled as a tree growing problem. Then a combination of list and force-directed scheduling algorithms is adapted to tackle it. ... View full abstract»

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  • The hierarchical timing pair model

    Publication Year: 2001, Page(s):367 - 370 vol. 5
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB) | HTML iconHTML

    We present a new model for representing timing information for functions in High-Level Synthesis (HLS). We identify shortcomings of the conventional timing model, which is a very simple model derived from the combinational logic model, and show that our new model overcomes many of these defects. In particular, we are able to provide a unified timing model that describes hierarchical combinational ... View full abstract»

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  • Author index

    Publication Year: 2001, Page(s):539 - 552
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  • Deriving accurate ASIC cell fault models for VITAL compliant VHDL simulation

    Publication Year: 2001, Page(s):263 - 266 vol. 5
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB) | HTML iconHTML

    This paper introduces a system for deriving accurate, technology specific fault models using analog defect simulation. It is implemented by a new software tool that provides a push-button solution for the tedious task of obtaining accurate ASIC cell defect to fault mappings. After completion of the cell defect analysis, the tool generates VITAL compliant, defect-injectable, VHDL cell models. These... View full abstract»

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  • Open ended dynamic ramping simulation of multi-discipline systems

    Publication Year: 2001, Page(s):307 - 310 vol. 5
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB) | HTML iconHTML

    The method described in this paper is a variant of a continuation method. The method enables finding a DC solution using a Dynamic Ramping (also called a “Pseudo Transient” analyses) for circuits where the settling time is not known in advance and is difficult to estimate. The method relies on the nonlinear solution algorithm for proper selection of the time step and for the detection ... View full abstract»

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  • Low-complexity and high quality frame-skipping transcoder

    Publication Year: 2001, Page(s):29 - 32 vol. 5
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB) | HTML iconHTML

    Transcoding is a process of converting a previously compressed video bitstream into a lower bit-rate bitstream. When some incoming frames are dropped for the frame-rate conversion in transcoding, the newly quantized DCT coefficients of prediction error need to be re-computed. In this paper, we propose a new architecture for low-complexity frame-rate reduction. The proposed algorithm is mainly perf... View full abstract»

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  • An AVPG for SOC design verification with port order fault model

    Publication Year: 2001, Page(s):259 - 262 vol. 5
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB) | HTML iconHTML

    Embedded cores are being increasingly used in the design of large system-on-a chip (SoC). Because the high complexity of SoC, the design verification is a challenge for system integrator. To reduce the verification complexity, the port order fault (POF) model has been used for verifying the core-based design. In this paper, we present a verification scheme and an automatic verification pattern gen... View full abstract»

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  • ST: PERL package for simulation and test environment

    Publication Year: 2001, Page(s):89 - 92 vol. 5
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB) | HTML iconHTML

    We propose a simulation and test environment called Perl package for Simulation and Test (ST). ST provides an environment to describe unified testbenches for various simulation levels. ST also supports LSI testers. ST is implemented as a Perl package. You can write your testbench according to the Perl syntax. ST supports simulators such as Verilog or SPICE. Expected vectors can be compared with si... View full abstract»

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  • Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint

    Publication Year: 2001, Page(s):519 - 522 vol. 5
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB) | HTML iconHTML

    In this paper, we propose a low power driven re-synthesis algorithm for LUT-based heterogeneous FPGA under delay constraint. We start with a delay optimal solution by using HeteroMap. The solution is then processed to reduce the power consumption and the circuit delay is held. Experimental results show that power consumption of the original mapping solution has been reduced by 15.02%. In addition,... View full abstract»

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  • Design methodology for optimization of analog building blocks using genetic algorithms

    Publication Year: 2001, Page(s):435 - 438 vol. 5
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB) | HTML iconHTML

    This paper presents an equation-based design methodology for optimization of analog building blocks using genetic algorithms. The proposed methodology uses the analytical equations that describe the circuit's behavior as a function of the design parameters such as the transistor dimensions and/or the passive component values. These parameters are then subject to an optimization process, using gene... View full abstract»

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  • Improved halftone image data hiding with intensity selection

    Publication Year: 2001, Page(s):243 - 246 vol. 5
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB) | HTML iconHTML

    In this paper, we propose a novel algorithm called intensity selection (IS) that can be applied to three existing halftone image data hiding algorithms DHST, DHPT and DHSPT to achieve improved visual quality. The proposed IS algorithm generalizes the hidden data representation and select the best location out of a set of candidate locations for the application of DHST/DHPT/DHSPT. It chooses pixel ... View full abstract»

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  • Wireless video conferencing using multiple description coding

    Publication Year: 2001, Page(s):303 - 306 vol. 5
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB) | HTML iconHTML

    The transmission of video over wireless is a particularly involved problem-requiring as it does the transmission of a variable length highly compressed, delay-sensitive stream over an error prone medium. In this paper, this problem is addressed within the multiple description coding paradigm. In particular the problem of wireless video conferencing over a constant bit-rate channel is addressed. A ... View full abstract»

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  • Transcoder with arbitrarily resizing capability

    Publication Year: 2001, Page(s):25 - 28 vol. 5
    Cited by:  Papers (19)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB) | HTML iconHTML

    This paper presents a transcoding technique that possesses the capability of arbitrarily resizing. Arbitrarily resizing is necessary when the resolution of an end display device differs from that of the video being pre-encoded. It is also a good strategy to achieve better visual quality when the transmission bandwidth is limited. The two key steps for a superior transcoding are the resizing and th... View full abstract»

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  • Tight coupling of timing-driven placement and retiming

    Publication Year: 2001, Page(s):351 - 354 vol. 5
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB) | HTML iconHTML

    Retiming is a widely investigated technique for performance optimization. In general, it performs extensive modifications on a circuit netlist, leaving it unclear whether the achieved performance improvement will still be valid after placement has been performed. This paper presents an approach for integrating retiming into a timing-driven placement environment. The experimental results show the b... View full abstract»

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  • An efficient BIST method for testing of embedded SRAMs

    Publication Year: 2001, Page(s):73 - 76 vol. 5
    Cited by:  Papers (18)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB) | HTML iconHTML

    We have developed an algorithm to enable conventional microprocessors to test their on-chip SRAM using their existing hardware and software resources. This test method utilizes a mixture of existing memory testing techniques, which cover all important memory faults. This is achieved by writing a routine called BIST Program which only uses the existing ROM and creates no additional hardware overhea... View full abstract»

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  • Top-down analog design methodology using Matlab and Simulink

    Publication Year: 2001, Page(s):319 - 322 vol. 5
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB) | HTML iconHTML

    This paper presents a new design methodology, featuring top-down design techniques in conjunction with an optimization process for the creation of analog or mixed signal integrated circuits. As a result, the requirements of the building blocks are specified prior to the undertaking of transistor level simulations, saving valued design time. This method has the advantage that designs can be impleme... View full abstract»

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  • Wireless video transport using conditional retransmission and low-delay interleaving

    Publication Year: 2001, Page(s):101 - 104 vol. 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB) | HTML iconHTML

    We consider the scenario of using Automatic Repeat reQuest (ARQ) retransmission for two-way low-bit-rate video communications over wireless Rayleigh fading channels. A low-delay constraint may require that a corrupted retransmitted packet not be retransmitted again, thus there will be packet-errors at the decoder which results in video quality degradation. In this paper. We propose a scheme to imp... View full abstract»

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  • Low-power multiplexer decomposition by suppressing propagation of signal transitions

    Publication Year: 2001, Page(s):85 - 88 vol. 5
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB) | HTML iconHTML

    Most circuits contain a number of multiplexers. An n-to-1 multiplexer is generally implemented by decomposition into 2-to-1 multiplexer. Due to its ordered tree structure, the n-to-1 multiplexer decomposition problem can be relatively easily solved for minimizing design considerations such as timing, area, and power consumption. In this paper, we propose an efficient and accurate method for estima... View full abstract»

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  • Implementation of hot-carrier reliability simulation in Eldo

    Publication Year: 2001, Page(s):515 - 518 vol. 5
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    The implementation of all components of hot-carrier reliability simulation in Eldo is described in this paper. A repetitive simulation scheme has been adopted to ensure accurate prediction of the circuit-level degradation process under dynamic operating conditions. Two approaches for modeling the degraded MOS transistor have been implemented, namely, the parameter fitting method and a newly propos... View full abstract»

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  • Hierarchical performance optimization for synthesis of linear analog systems

    Publication Year: 2001, Page(s):431 - 434 vol. 5
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB) | HTML iconHTML

    This paper presents a hierarchical performance optimization method for high level synthesis of analog systems. The goal is to minimize silicon area while meeting design constraints i.e. AC behavior, op amp gains, slew-rate, power etc. The technique is organized as two successive steps: (1) gain distribution for assigning gains to circuits; and (2) actual performance optimization for finding design... View full abstract»

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  • Embedding gray level images

    Publication Year: 2001, Page(s):239 - 242 vol. 5
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB) | HTML iconHTML

    Hiding a gray scale image encounters some difficulties. In this paper, a DCT-based image hiding algorithm is proposed. The bit rate of the hidden image is reduced by applying an image compression technique. To extract the hidden data from the corrupted watermarked image, BCH coding and matched filtering are applied. With the proposed algorithm, we hide a gray scale image of 64×64×8 in ... View full abstract»

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  • Area(number)-balanced hierarchy of staircase channels with minimum crossing nets

    Publication Year: 2001, Page(s):395 - 398 vol. 5
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB) | HTML iconHTML

    We address the problem of hierarchically partitioning a VLSI floorplan F using monotone staircase channels to aid global routing. Our problem is to identify a monotone staircase channel (ms-cut) from one corner of F to its opposite corner, such that (i) the number of nets crossing the ms-cut is minimized, and (ii) the area (or the number of the blocks) of both the partitions are nearly equal. The ... View full abstract»

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  • An embedded wavelet-based quadtree interframe coding algorithm

    Publication Year: 2001, Page(s):299 - 302 vol. 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB) | HTML iconHTML

    Motion compensated prediction (MCP) error image has significant amplitudes mainly along the boundaries of moving objects, correspondingly its wavelet coefficients contain large energy in high frequency bands. This greatly reduces the coding efficiency of embedded zerotree wavelet (EZW) coding. In this paper, we first provide the correspondence between the significant amplitudes area of the MCP err... View full abstract»

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