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Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001

14-16 March 2001

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  • Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001

    Publication Year: 2001
    Request permission for commercial reuse | PDF file iconPDF (133 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 2001, Page(s): 265
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    Freely Available from IEEE
  • A low-power asynchronous VLSI FIR filter

    Publication Year: 2001, Page(s):29 - 39
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB) | HTML iconHTML

    An asynchronous FIR filter, based on a single bit-plane architecture with a data-dependent, dynamic-logic implementation, is presented. Its energy consumption and sample computation delay are shown to correlate approximately linearly with the total number of ones in its coefficient-set. The proposed architecture has the property that coefficients in a sign-magnitude representation can be handled a... View full abstract»

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  • Analog-digital partitioning for field-programmable mixed signal systems

    Publication Year: 2001, Page(s):172 - 185
    Cited by:  Papers (2)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB) | HTML iconHTML

    Synthesis of mixed-signal designs from behavioral specifications must address analog-digital partitioning. In other words, determining what portions of the design are best implemented using analog and digital circuitry. In this work, we target reconfigurable mixed-signal systems composed of field-programmable analog and digital arrays. These field-programmable systems are invaluable for rapid hard... View full abstract»

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  • Precise exceptions in asynchronous processors

    Publication Year: 2001, Page(s):16 - 28
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB) | HTML iconHTML

    The presence of precise exceptions in a processor leads to complications in its design. Some recent processor architectures have sacrificed this requirement for performance reasons at the cost of software complexity. We present an implementation strategy for precise exceptions in asynchronous processors that does not block the instruction fetch when exceptions do not occur; the cost of the excepti... View full abstract»

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  • A high-performance 64-bit adder implemented in output prediction logic

    Publication Year: 2001, Page(s):213 - 222
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB) | HTML iconHTML

    Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the restoring character of the logic family. Speedups of 2× to 3× over (optimized) conventional static CMOS are demonstrated for a variety of circuits, ranging from chains of gates, to datapath circuits, and to ra... View full abstract»

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  • Visual sensor with resolution enhancement by mechanical vibrations

    Publication Year: 2001, Page(s):249 - 264
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (968 KB) | HTML iconHTML

    The resolution limit of visual sensors due to finite pixel spacing can be overcome by applying continuous low-amplitude vibrations to the image-or taking advantage of existing vibrations in the environment, for instance in a mobile robotics application. Thereby, spatial intensity gradients turn into temporal intensity fluctuations which can be detected and processed by every pixel independently fr... View full abstract»

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  • Dynamic charge restoration of floating gate subthreshold MOS translinear circuits

    Publication Year: 2001, Page(s):163 - 171
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB) | HTML iconHTML

    We extend a class of analog CMOS circuits that can be used to perform many analog computational tasks. The circuits utilize MOSFETs in their subthreshold region as well as capacitors and switches to produce the computations. We show a few basic current mode building blocks that perform squaring, square root, and multiplication/division which should be sufficient to gain understanding of how to imp... View full abstract»

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  • Width-adaptive data word architectures

    Publication Year: 2001, Page(s):112 - 129
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (976 KB) | HTML iconHTML

    We discuss number representations for width-adaptive data word architectures. The number representations are self-delimiting, permitting asynchronous implementations with dynamic width adaptivity and reduced energy-complexity. We describe how these architectures can be realized with asynchronous VLSI techniques, and show that they exhibit better energy and throughput characteristics than tradition... View full abstract»

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  • Building a distributed asynchronous control unit through automatic derivation of hierarchically decomposed AFSMs from a CDFG

    Publication Year: 2001, Page(s):2 - 15
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB) | HTML iconHTML

    Although there are several successful asynchronous logic synthesis tools, it is still unwieldy for designers to conceive and describe behaviors for a number of controllers constituting an asynchronous control unit of a target system manually. In this paper, building a distributed asynchronous control unit automatically through automatic derivation of hierarchically decomposed AFSMs from a CDFG is ... View full abstract»

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  • Activity-sensitive flip-flop and latch selection for reduced energy

    Publication Year: 2001, Page(s):59 - 74
    Cited by:  Papers (13)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (764 KB) | HTML iconHTML

    This article presents new techniques to evaluate the energy and delay of flip-flop and latch designs and shows that no single existing design performs well across the wide range of operating regimes present in complex systems. We prepose the use of a selection of flip-flop latch designs, each timed for different activation patterns and speed requirements. We illustrate the use of our technique on ... View full abstract»

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  • Asynchronous array multiplier with an asymmetric parallel array structure

    Publication Year: 2001, Page(s):202 - 212
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB) | HTML iconHTML

    In this paper an asynchronous array multiplier with a new parallel structure is introduced. This parallel array structure is designed to make the computation time faster with lower power consumption. An asymmetric array structure is used to minimize the average computation time in an asynchronous multiplier. Simulation shows that this structure reduces the time needed for computation by 55% as com... View full abstract»

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  • Methods and circuits for focal-plane computation of features in CMOS visual sensors

    Publication Year: 2001, Page(s):238 - 248
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (736 KB) | HTML iconHTML

    Feature detection, and tracking is a fundamental problem in computer vision research. By detecting and tracking features in an image sequence it is possible to recover information about both the motion of the viewer and the structure of the environment. The selection of features is a computationally intensive task. We derive two low-complexity algorithms that are suitable for integration in a CMOS... View full abstract»

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  • Programmable and adaptive analog filters using arrays of floating-gate circuits

    Publication Year: 2001, Page(s):148 - 162
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (840 KB) | HTML iconHTML

    In this paper we describe a programmable and adaptive filter based on floating-gate technology We review the basics of floating-gate techniques and how they enable programmable and adaptive filter circuits. We describe our programmable filter concepts, and show experimental results of programmable filter operation. We also describe programming methods, and extend the programmability to a wide rang... View full abstract»

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  • Dynamic receiver biasing for inter-chip communication

    Publication Year: 2001, Page(s):101 - 111
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB) | HTML iconHTML

    A noise cancellation circuit was designed to improve the performance of a single-ended source-synchronous I/O interface. Common-mode variations between the high-frequency data bits and the DC reference against which they are compared were nulled using negative feedback. The clock and its complement were filtered at the receiving chip to establish an average value, which corresponds to duty cycle. ... View full abstract»

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  • Design, verification, and test of a true single-phase 8-bit adiabatic multiplier

    Publication Year: 2001, Page(s):42 - 58
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (900 KB) | HTML iconHTML

    In this paper we present the design and experimental evaluation of an an 8-bit adiabatic multiplier with built-in self-test (BIST) logic and an internal single-phase sinusoidal power-clock generator: Both the multiplier and the BIST have been designed in SCAL-D, a true single-phase adiabatic logic family. In HSPICE simulations with post-layout extracted parasitics, our design functions correctly a... View full abstract»

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  • A standard-cell self-timed multiplier for energy and area critical synchronous systems

    Publication Year: 2001, Page(s):188 - 201
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB) | HTML iconHTML

    This paper describes the design of a standard-cell self-timed multiplier for use in energy and area critical synchronous systems. The area of this multiplier is bounded by N rather than N2 as seen in more traditional combinational parallel array designs, where N is the word size. Energy has a polynomial growth with word size, but has a coefficient that is much smaller than that seen in ... View full abstract»

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  • Focal-plane image and beam quality sensors for adaptive optics

    Publication Year: 2001, Page(s):224 - 237
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (828 KB) | HTML iconHTML

    Control of adaptive optical elements for real-time wavefront phase distortion compensation is a rapidly growing field of research and technology development. Wavefront correction is essential for reliable long distance, near-ground laser communication as well as for imaging extended objects over large distances. Crucial to adaptively correcting the wavefront is a performance metric that can be dir... View full abstract»

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  • Analog MAP decoder for (8, 4) Hamming code in subthreshold CMOS

    Publication Year: 2001, Page(s):132 - 147
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB) | HTML iconHTML

    An all-MOS analog implementation of a MAP decoder is presented for the (8, 4) extended Hamming code. This paper describes the design and analysis of a tail-biting trellis decoder implementation using subthreshold CMOS devices. A VLSI test chip has recently returned from fabrication, and preliminary test results indicate accurate decoding up to 20 MBit/s View full abstract»

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  • Logic design considerations for 0.5-volt CMOS

    Publication Year: 2001, Page(s):75 - 85
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB) | HTML iconHTML

    As the operation supply voltage for commercial CMOS devices falls below 2 V, research activities are underway to develop CMOS integrated circuits that can operate at supply voltages well under 1 V. Although dramatic power reductions can be achieved using low supply voltages in high performance applications, the increased subthreshold leakage that results when transistor threshold voltages are lowe... View full abstract»

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  • Phantom mode signaling in VLSI systems

    Publication Year: 2001, Page(s):88 - 100
    Cited by:  Papers (7)  |  Patents (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB) | HTML iconHTML

    Differential signaling uses double the number of interconnects when compared to single ended signaling. The signal to interconnect usage of a differential signal is (n/2) balanced signals per n interconnects. A method is described which can increase the interconnect usage to (n-1) balanced signals per n wires. The additional bandwidth is achieved by inserting signal information into the common mod... View full abstract»

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