Quality Electronic Design, 2001 International Symposium on
Date 28-28 March 2001
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Displaying Results 1 - 25 of 76
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Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design
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PDF (488 KB)
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Compact layout rule extraction for latchup prevention in a 0.25-/spl mu/m shallow-trench-isolation silicided bulk CMOS process
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PDF (585 KB)
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Author index
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PDF (146 KB)
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High-quality FPGA designs through functional decomposition with sub-function input support selection based on information relationship measures
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PDF (587 KB)
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A compact layout technique for reducing switching current effects in high speed circuits
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PDF (658 KB)
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Test pattern generators for distributed and embedded built-in self-test at register transfer level
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PDF (315 KB)
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New efficient and accurate moment matching based model for crosstalk estimation in coupled RC trees
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PDF (563 KB)
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Memory hierarchy optimization of multimedia applications on programmable embedded cores
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PDF (542 KB)
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VSIA quality metrics for IP and SoC
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PDF (644 KB)
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Assessment of true worst case circuit performance under interconnect parameter variations
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PDF (531 KB)
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CAD issues for CMOS VLSI design in SOI
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PDF (561 KB)
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