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Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on

Date 25-27 Feb. 2001

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Displaying Results 1 - 25 of 35
  • 2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475)

    Publication Year: 2001
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    Freely Available from IEEE
  • Author index

    Publication Year: 2001 , Page(s): 173
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    Freely Available from IEEE
  • A digitally adjustable resistor for path delay characterization in high-frequency microprocessors

    Publication Year: 2001 , Page(s): 61 - 64
    Cited by:  Papers (14)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (284 KB) |  | HTML iconHTML  

    Most high-frequency microprocessors have a clock distribution network allowing the manipulation of the clock edges to facilitate silicon debug and path delay characterization. Typically, a particular edge of the clock is skewed using a variable-delay element until a failure occurs. This paper describes a digitally adjustable resistor applied to the construction of such a variable-delay element. The operation of the digitally adjustable resistor is explained. A strategy to choose the control bits for the resistor is also discussed. The proposed variable-delay element can achieve a 1-ps resolution over a 50-ps range in a 180-nm fabrication technology View full abstract»

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  • A highly linear BiCMOS down-conversion mixer with MCM passives for GPS applications

    Publication Year: 2001 , Page(s): 65 - 69
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB) |  | HTML iconHTML  

    The specification of today's wireless receivers are low noise figure, low power consumption, high linearity, and a high degree of integration. To meet these requirements at the system level, every RF block has to meet them. This paper presents a design of one of the RF blocks: a down-conversion mixer. The mixer uses MCM inductors as degeneration in the input differential pair, which yields it a high linearity (high IP3 voltage), a high input impedance and reduces noise. The high input impedance, together with the small required LO signal guarantees low power operation. This combination makes it well suited to integrate in a single-package GPS receiver View full abstract»

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  • An analog front-end for the acquisition of biomedical signals, fully integrated in a 0.8 μm CMOS process

    Publication Year: 2001 , Page(s): 152 - 157
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB) |  | HTML iconHTML  

    This work explores the feasibility of a cardiac pacemaker front-end, realized using a fully integrated solution. Particularly two different architectures for the sensing chain are compared. The first is based on an SC biquadratic cell and performs the minimum signal processing required, i.e. a band-pass filtering before peak detection. The second is based on a ΣΔ converter, allowing for more advanced pacing strategies. Both architectures require a low-noise pre-amplifier, realized as a log-domain filter, and pose typical challenges of low-voltage and low-power design. Both circuits, realized in 0.8 μm CMOS process, behave as required by the application and have a reduced power consumption. Hence the feasibility of fully-integrated solution is proved, for both sensing approaches, giving the possibility to drastically reduce pacemaker size View full abstract»

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  • Behavioral model of pipeline ADC by using SIMULINK(R)

    Publication Year: 2001 , Page(s): 147 - 151
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB) |  | HTML iconHTML  

    The presented work concentrates on behavioral modeling of pipeline ADCs. For this purpose the parameters that affect the operation of basic pipeline ADC blocks are investigated. The non-ideal parameters of these blocks are modeled by using MATLAB(R) and SIMULINK(R) View full abstract»

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  • Watermarking of standard-cell feedthroughs in mixed-signal design

    Publication Year: 2001 , Page(s): 121 - 125
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB) |  | HTML iconHTML  

    This paper presents a method for watermarking standard-cell designs in a mixed-signal design environment. The method utilizes the constraints that are placed on a mixed-signal standard-cell design in terms of routing layers, utilizing feedthroughs to watermark the standard-cell portion of the design. The design is watermarked by modifying placement of feedthroughs in the design, allowing the designer flexibility in their placement View full abstract»

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  • Power supply induced jitter modeling of an on-chip LC oscillator

    Publication Year: 2001 , Page(s): 132 - 136
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB) |  | HTML iconHTML  

    This paper concentrates on developing a closed-form small signal model to determine the power supply induced jitter (PSIJ) for on chip LC based voltage controlled oscillator (VCO). To determine the source of the PSIJ, we have developed a Mathcad model which is used to optimize the VCO design in order to achieve the lowest possible jitter allowed by its architecture View full abstract»

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  • A digitally controlled oscillator constructed using adjustable resistors

    Publication Year: 2001 , Page(s): 80 - 82
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB) |  | HTML iconHTML  

    Controlled oscillators have a significant impact on clock distribution in high-frequency microprocessors. This paper describes a novel digitally controlled oscillator (DCO) constructed using adjustable resistors. Its ping-pong architecture significantly reduces the jitter introduced when the control input is updated. The adjustable resistors digitally set the delay of each stage of a current-starved ring oscillator. The oscillator operates from 1.350 GHz to 4.550 GHz in a 180 nm fabrication technology View full abstract»

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  • Power-supply overvoltage protection circuit for motorcycle on-board electronics

    Publication Year: 2001 , Page(s): 162 - 166
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (316 KB) |  | HTML iconHTML  

    A simple circuit used to protect on-board electronics from power-supply overvoltages due to the electrical environment of motorcycles is presented in this paper. The circuit is integrated as a macrocell to be embedded in the on-board electronics in order to protect it from dangerous voltage levels (up to 200 V) on the power-supply. This choice avoids the use of any external component except a resistor and a capacitor. The circuit behaves as a non-linearly driven shunt switch, which turns the supply voltage off when activated. Its main features are avoiding a large power consumption on the power MOS shunt and allowing a reduced area occupation of it. The paper describes the circuit, presents simulation results and finally the experimental characterization of the prototype chips fabricated with a 2 μm CMOS high voltage (50 V) process View full abstract»

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  • A simple method for relating time- and frequency-domain measures of oscillator performance

    Publication Year: 2001 , Page(s): 7 - 12
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB) |  | HTML iconHTML  

    This paper presents a simple technique for linking time domain (jitter) and frequency domain (phase noise) measures of oscillator performance. The key concept is the definition of a single figure-of-merit in the time- or frequency-domain that relates system-level performance (such as jitter or phase noise) to circuit-level parameters (such as power dissipation and signal amplitude). This technique is particularly applicable to circuit- and system-level design of voltage-controlled oscillators (VCOs) and phase-locked loops (PLLs). The technique allows VCO and PLL design and characterization to take place in the domain (time or frequency, PLL open-loop or closed-loop) that provides the most insight into sources of jitter, while allowing a direct link to system-level performance as measured in any other domain. The methodology also speeds simulation since only the open loop VCO need be simulated, which allows a substantial savings in simulation time. Design examples and experimental results are presented for existing PLLs showing good agreement to the theoretical predictions View full abstract»

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  • Mixed signal DFT/BIST automation using behavioral modeling

    Publication Year: 2001 , Page(s): 137 - 140
    Cited by:  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB) |  | HTML iconHTML  

    One of the hurdles in mixed signal built in self test is automation. This paper presents a robust mixed signal design for test and built in self test library based approach for BIST circuit creation, insertion, verification and test pattern generation that fits into the existing design flow View full abstract»

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  • Automated power supply noise reduction via optimized distributed capacitors insertion

    Publication Year: 2001 , Page(s): 167 - 172
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB) |  | HTML iconHTML  

    Phenomena like IR drop, L dI/dt, electromigration and crosstalk are menacing in increasing proportions ultra deep submicron ICs functionality. This is a consequence of their growing complexity driven by increased speed, size, and interconnect density due to technology scaling down and high metal levels number used. The related consequences are delays, errors and failures, and depend on the global number, position and connections among gates. The correct approach to face the solution of these problems must be global and not local to a single gate. Having such a global prospect is easy at the end of a design flow, but leads to an expensive trial and error methodology: an alternative is facing early in the design sequence the potential noise generation of a circuit block. This paper focuses on a power supply model such as each gate connected to the power busses has an integrated capacitor automatically generated to reduce simultaneous switching noise. This model has been inserted in a developing tool for interconnect parameters prediction and noise safety design View full abstract»

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  • An improved current-mode CMOS voltage reference

    Publication Year: 2001 , Page(s): 23 - 27
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB) |  | HTML iconHTML  

    An improved current-mode CMOS voltage reference derives its temperature independent characteristic from two temperature dependent currents which are summed together into a resistor to generate the reference voltage. A CMOS proportional to absolute temperature (PTAT) current generator using substrate bipolar transistors creates the current that increases with temperature. A CMOS threshold voltage extractor circuit creates the conversely proportional to absolute temperature (CTAT) current that decreases with increasing temperature. The reference operates over a temperature range of 0 to 100°C with a power supply voltage between 3.3 and 7 V. Simulations show that over these conditions, the output voltage varies by less than 1% over the specified temperature range while using less than 75 μA of current View full abstract»

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  • A methodology for sinusoidal oscillator design to adjust for amplifier slew rate and bandwidth limitations

    Publication Year: 2001 , Page(s): 83 - 86
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB) |  | HTML iconHTML  

    This work develops a methodology to position the oscillation frequency close to the maximum usable bandwidth of an operational amplifier. A practical example using the LF351 operational amplifier with an fT=4 MHz illustrates the methodology. A sinusoidal 440 kHz oscillator with a 1 Vp-p amplitude produced a total harmonic distortion of 1.33% and a phase noise of -65 dBc at 1 kHz offset View full abstract»

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  • Numerical modeling of PLL jitter and the impact of its non-white spectrum on the SNR of sampled signals

    Publication Year: 2001 , Page(s): 38 - 44
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB) |  | HTML iconHTML  

    The impact of PLL jitter on ADC systems is nowadays mainly investigated performing numerical simulation at system level using a Gaussian white distributed noise source. The “colored” characteristic of the jitter spectrum of PLLs is thus completely neglected. We present some practical considerations on the impact of a non-white spectrum jitter on the SNR of an analog to digital conversion. A simple numerical model is developed, which can be used for simulating the impact of non-white and “sinusoidally modulated” noise on sampling system. This model is applied to a simple ADC system and to a QAM receiver. This analysis will help to understand which is the relevant jitter specification for analog to digital conversion systems View full abstract»

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  • A fully integrated 8-bit, 20 MHz, truly random numbers generator, based on a chaotic system

    Publication Year: 2001 , Page(s): 87 - 92
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (412 KB) |  | HTML iconHTML  

    This work proposes a fully integrated random numbers generator. A chaotic system has been chosen as a source of randomness, in order to grant statistical independence and uniform distribution to the 8-bit generated words. An effective and compact architecture, based on a pipeline ADC only, has been singled out and realized in a standard 0.8 μm CMOS process. Particularly main circuit non-idealities have been properly managed, in order to enhance the statistical properties of the generated numbers. The randomness has been proved and quantified by post-layout simulations. Finally the circuit occupies 2.2 mm2 of silicon area and dissipates 50 mW when clocked at 20 MHz View full abstract»

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  • Effects of integrated circuit packaging on performance of a LNA in a mixed-signal circuit environment

    Publication Year: 2001 , Page(s): 76 - 79
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB) |  | HTML iconHTML  

    Low cost and low packing densities are the most important considerations in design and manufacture of modern electronics. This has resulted in new design tools and electrical analysis tools for this new generation of circuits. This design technology is called mixed-signal design. The packages used for such applications are the high end, high I/O pin packages, which have considerably smaller package impedance to reduce power dissipation in the package and also trace lengths are much smaller so as to reduce coupling between adjacent signal lines. Ball Grid Array (BGA) packages along with other Chip Scale Packages (CSP) are the packages of choice for high end, high I/O packages. Certain high I/O Small Outline Packages (SOP) are also being used for such applications. Different package types provide different amounts of crosstalk through different components that makeup an integrated circuit package. Substrate coupling noise along with the package parasitic associated with packages used for these applications is the center of study in this paper View full abstract»

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  • A novel automatic tuning scheme for high-frequency high-Q continuous-time filters

    Publication Year: 2001 , Page(s): 126 - 130
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB) |  | HTML iconHTML  

    An automatic tuning scheme for high-frequency high-Q continuous time biquadratic filters is proposed. The method is based on tuning the slope of the phase response around the pole frequency. The value of Q is digitally controlled and does not depend on the filter's bandpass gain, which may be quite different than Q in the presence of dominant parasitics. Therefore, very high-frequency high-Q filters can be tuned accurately. Digital phase locked loops and frequency dividers are employed by the tuning circuit View full abstract»

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  • High speed re-configurable pipeline ADC cell design

    Publication Year: 2001 , Page(s): 158 - 161
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB) |  | HTML iconHTML  

    The design and implementation of a high speed reconfigurable pipeline ADC cell is presented in this paper. Each cell in the pipeline can be a sample and hold gain of 1 stage, or gain of 2 as multiplying by 2 stage, or gain of 1.9 stage capable of doing calibration. The design is implemented in TSMC 0.25 μm single-poly CMOS digital process View full abstract»

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  • General SSCR vs. cycle-to-cycle jitter relationship with application to the phase noise in PLL

    Publication Year: 2001 , Page(s): 32 - 37
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (448 KB) |  | HTML iconHTML  

    In this work we derive a general formula to link the phase noise rated via the cycle-to-cycle jitter of the oscillation period, to the single sideband to carrier ratio (SSCR). The validity of the relationship between the time- and frequency-domain figures of merit has been first tested through the simulation of a widely popular case: the phase noise spectrum featured by PLL synthesizers. As a further proof, measurements have also been performed on CMOS and bipolar integrated VCOs and PLLs, by adopting time-to-amplitude conversion techniques View full abstract»

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  • Gate recognition and netlist reduction for switch-level simulation of dynamic bit-level systolic arrays

    Publication Year: 2001 , Page(s): 56 - 60
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB) |  | HTML iconHTML  

    A program for gate recognition has been developed and used to reduce the netlist produced by layout flat extraction of a 1.2 million transistor bit-level systolic array design. The pipeline dynamic flip-flops as well as other elemental structures typical of systolic arrays are recognized. The netlist was reduced by a factor 8, thus allowing a post-layout switch-level simulation of the whole chip, otherwise impossible on the original netlist View full abstract»

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  • Noise analysis of monolithic RF balanced down conversion mixers

    Publication Year: 2001 , Page(s): 70 - 75
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (304 KB) |  | HTML iconHTML  

    In this paper, noise features of monolithic RF balanced down conversion mixers are examined and analysed in detail with a periodic steady state simulator. The three kinds of port matching circuit architecture are proposed. Applying these optimum architectures to the single and double balanced down conversion (SBDC and DBDC) mixers can largely improve the mixers' performance. The valuable reference parameters were given in order to design low noise, low power consumption and high performance mixers. The validated mixers were designed by using a 25 GHz Si bipolar technology, which is under 2.7 V power supply, RF at 5.8 GHz, and IF at 100 MHz and 1 GHz, respectively. The conversion gain is better than 0 dB. The noise figure is lower 10 dB View full abstract»

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  • A front-end filter with automatic center frequency tuning circuitry

    Publication Year: 2001 , Page(s): 28 - 31
    Cited by:  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB) |  | HTML iconHTML  

    A new automatic tuning circuit based on synchronous rectification scheme is proposed. The direct tuning circuit functions in the idle periods between the burst-mode transmissions. The proposed CMOS tuning circuit can be fully integrated with the front-end filter. Simulation results employing 0.5 μm CMOS technology have verified that the center frequency is automatically tuned to 1.25 GHz with 10% process variation presence. The deviation is 15 MHz, representing to only 1.2% error. The tuning circuit dissipates 34 mW power View full abstract»

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  • Noise in phase-locked loops

    Publication Year: 2001 , Page(s): 1 - 6
    Cited by:  Papers (32)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (492 KB) |  | HTML iconHTML  

    Jitter and phase noise properties of phase-locked loops (PLL) are analyzed, identifying various forms of jitter and phase noise in PLLs. The effects of different building blocks on the jitter and phase noise performance of PLLs are demonstrated through a parallel analytical and graphical treatment of noise evolution in the phase-locked loop View full abstract»

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