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Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)

2-2 Feb. 2001

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  • Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)

    Publication Year: 2001
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    Freely Available from IEEE
  • Reusable embedded in-circuit emulator

    Publication Year: 2001, Page(s):33 - 34
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    In this paper, we introduce the Reusable Embedded In-Circuit Emulator (EICE) and Reusable EICE development system. The main functions of the EICE we designed are testing and debugging. The architecture of EICE is reusable and based on the IEEE 1149.1 boundary scan architecture. The EICE development system can help EICE to reduce the development time for a microcontroller/microprocessor. We impleme... View full abstract»

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  • Author index

    Publication Year: 2001, Page(s):669 - 674
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    Freely Available from IEEE
  • Reducing cache energy through dual voltage supply

    Publication Year: 2001, Page(s):302 - 305
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB) | HTML iconHTML

    Due to a large capacitance and enormous access rate, caches dissipate about a third of the total energy consumed by today's processors. In this paper we present a new architectural technique to reduce energy consumption in caches. Unlike previous approaches, which have focused on lowering cache capacitance and the number of accesses, our method exploits a new freedom in cache design, namely the vo... View full abstract»

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  • An on-chip 96.5% current efficiency CMOS linear regulator

    Publication Year: 2001, Page(s):297 - 301
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB) | HTML iconHTML

    A proposed linear regulator uses a flexible control technique of output current (FCOC) to achieve 96.5% efficiency. The FCOC technique drives a flexible output current according to the output current variation and stable output voltage supply. The linear regulator fabricated by 1.2 μm CMOS process occupies 0.423 mm2. The fabricated linear regulator achieves 96.5% current efficiency a... View full abstract»

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  • Low power design challenges for the decade

    Publication Year: 2001, Page(s):293 - 296
    Cited by:  Papers (32)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB) | HTML iconHTML

    Technology scaling will become difficult beyond 0.18 micron. For continued growth in performance, transistor density, and reduced energy per computation, circuit design will have to employ a new set of design techniques, with adequate design automation tools support. This paper discusses a few such techniques that reduce active and leakage power, and deliver higher performance. It concludes by poi... View full abstract»

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  • A mixed-signal simulator for VHDL-AMS

    Publication Year: 2001, Page(s):287 - 291
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB) | HTML iconHTML

    Capable and efficient simulators are in demand for designing complex analog and mixed-signal circuits and systems. With the standardization of VHDL-AMS, the demand is being realized. VHDL-AMS is an analog and mixed-signal extension to VHDL. This paper introduces a mixed-signal simulator for it. The simulator was developed on the original VHDL digital simulation environment. An analog kernel has be... View full abstract»

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  • Efficient minimum spanning tree construction without Delaunay triangulation [VLSI CAD]

    Publication Year: 2001, Page(s):192 - 197
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB) | HTML iconHTML

    Minimum spanning tree problem is a very important problem in VLSI CAD. Given n points in a plane, a minimum spanning tree is a set of edges which connects all the points and has a minimum total length. A naive approach enumerates edges on all pairs of points and takes at least Ω(n2) time. More efficient approaches find a minimum spanning tree only among edges in the Delaunay trian... View full abstract»

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  • Device-level placement for analog layout: an opportunity for non-slicing topological representations

    Publication Year: 2001, Page(s):281 - 286
    Cited by:  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB) | HTML iconHTML

    Layout design for analog circuits has historically been a time consuming, error-prone, manual task. Its complexity results not so much from the number of devices, as from the complex interactions among devices or with the operating environment, and also from continuous-valued performance specifications. This paper addresses the problem of device-level placement for analog layout in a non-tradition... View full abstract»

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  • A 3-step approach for performance-driven whole-chip routing

    Publication Year: 2001, Page(s):187 - 191
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB) | HTML iconHTML

    We propose a 3-step approach for whole-chip detail routing. In the first step, we construct a performance-driven Steiner tree for each net ignoring the existence of other nets. In the second step, we optimally assign significant wire segments of all trees to the tracks of a two-dimensional, two-layer grid under the design rule constraint. Finally, in the third step, we complete the remaining local... View full abstract»

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  • Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits

    Publication Year: 2001, Page(s):437 - 442
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB) | HTML iconHTML

    The quasi-delay-insensitive (QDI) model assumes that all the forks are isochronic. The isochronic-fork assumption requires uniform wire delays and uniform switching thresholds of the gates associated with the forking branches. This paper presents a method for determining such forks that do not have to satisfy the isochronic fork requirements, and presents experimental results that show many isochr... View full abstract»

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  • A dynamically phase adjusting PLL with a variable delay

    Publication Year: 2001, Page(s):275 - 280
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB) | HTML iconHTML

    Phase locked loops (PLLs) are widely used for many purposes. The lock-up performance is one of the most important target items in designing PLLs. In a digital PLL, it is difficult to control the frequency and phase independently, which makes it difficult to improve lock-up performance. A variable delay circuit which adjusts only the phase of the PLL is introduced here. A full loop model simulation... View full abstract»

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  • An efficient solution to the storage correspondence problem for large sequential circuits

    Publication Year: 2001, Page(s):181 - 186
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB) | HTML iconHTML

    Traditional state-traversal-based methods for verifying sequential circuits are computationally infeasible for circuits with a large number of memory elements. However, if the correspondence of the memory elements of the two circuits can be established, a difficult sequential verification problem can be transformed into an easier combinational verification problem. In this paper, we propose an app... View full abstract»

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  • Flexible processor based on full-adder/D-flip-flop merged module

    Publication Year: 2001, Page(s):35 - 36
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB) | HTML iconHTML

    Flexible processor based on full-adder/D-flip-flop merged module (FDMM) has been designed and fabricated. The developed FDMM has unique ability to perform both logic and flip-flop functions with a small transistor count by merging the common part of both circuits. We have also developed a context memory block to reconfigure the hardware dynamically. The flexible processor may fill a gap between ha... View full abstract»

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  • High-level design for asynchronous logic

    Publication Year: 2001, Page(s):431 - 436
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB) | HTML iconHTML

    Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete high level design flow for asynchronous circuits based on register transfer level (RTL) VHDL using commercial simulation and synthesis tools. Contrary to previous asynchronous approaches, the proposed RTL methodology closely res... View full abstract»

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  • A higher level system communication model for object-oriented specification and design of embedded systems

    Publication Year: 2001, Page(s):69 - 77
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (892 KB) | HTML iconHTML

    The design starting point for current embedded systems design is getting higher and higher on the abstraction level scale in order to meet the challenge of the increasing design gap. Up to now the state-of-the-art tools and methods have used as a highest abstraction of communication for the send-receive over a channel, e.g. as in SDL and COSSAP. We introduce a novel higher level communication mech... View full abstract»

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  • A pipelined ADC macro design for multiple applications

    Publication Year: 2001, Page(s):269 - 274
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB) | HTML iconHTML

    We present a new design methodology for high-speed analog-to-digital converter (ADC) macros based on our original pipelined 10-bit ADC. With library re-use methodology and performance driven optimization techniques, we have been able to both shorten the design period and to meet application specifications for items such as speed and power consumption. Using this method, we have developed ADC macro... View full abstract»

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  • Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers

    Publication Year: 2001, Page(s):175 - 180
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB) | HTML iconHTML

    Formal verification plays an important role in the verification of complex processors. In this paper, we discuss the usage and impact of equivalence checking in the verification of TI's TMS320C27X DSP core. During various phases of the design, we need to ensure the correctness of the design, a significant part of which could be best done with an equivalence checker. (For example, verifying the fun... View full abstract»

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  • Formal verification of pulse-mode asynchronous circuits

    Publication Year: 2001, Page(s):347 - 352
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB) | HTML iconHTML

    This paper addresses the problem of verifying pulse-mode asynchronous circuits, which combine advantages of different asynchronous design styles. A novel technique is proposed for constructing in a modular manner specifications and functional models of pulse-mode circuits. Case studies show the feasibility of formal verification on the basis of the proposed construction, integrated into an existin... View full abstract»

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  • Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks

    Publication Year: 2001, Page(s):231 - 234
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB) | HTML iconHTML

    In some modern FPGAs and CPLDs, PLA (programmable logic array)-style logic blocks can be used as the storage elements for improved logic density and performance. PLA-style logic blocks were originally deployed in the early PLDs. Due to recent research developments in the FPGA community, PLA-style logic blocks are becoming an effective storage alternative in FPGAs. This paper presents an approach w... View full abstract»

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  • Integrated power supply planning and floorplanning

    Publication Year: 2001, Page(s):589 - 594
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB) | HTML iconHTML

    One of the most challenging issues in today's high-performance VLSI design is to ensure high-quality power supply to each individual circuit blocks. Reduced power supply voltage can result in slower cell switching, or even circuit failure. Nevertheless, most floorplanning methodologies have ignored power supply considerations. Thus, the resulting floorplan may suffer from local hot spots and insuf... View full abstract»

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  • Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs

    Publication Year: 2001, Page(s):425 - 430
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB) | HTML iconHTML

    We propose a method of synthesizing pipeline controllers as four-phase asynchronous circuits from specifications described as two-phase dependency graphs. Pipeline two-phase dependency graphs are transformed into four-phase ones by applying a transformation rule to each simple loop in the graphs. Four-phase dependency graphs are easily mapped onto four-phase asynchronous control circuits. We also ... View full abstract»

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  • Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures

    Publication Year: 2001, Page(s):63 - 68
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB) | HTML iconHTML

    In this paper, we present a cosimulation environment that provides modularity, scalability, and flexibility in cosimulation of SoC designs with heterogeneous multi-processor target architectures. Our cosimulation environment is based on an object-oriented simulation environment, SystemC. Exploiting the object orientation in SystemC representation, we achieve modularity and scalability of cosimulat... View full abstract»

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  • Imprecise data computation for high performance asynchronous processors

    Publication Year: 2001, Page(s):261 - 266
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB) | HTML iconHTML

    Instruction level parallelism (ILP) is strictly limited by various dependencies. In particular, data dependency is the major performance bottleneck of data intensive applications. To accelerate the execution of sequential code serialized due to data dependencies, this paper proposes an imprecise computation as a fast data computing technique for a high-performance asynchronous processor. To show t... View full abstract»

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  • Equivalence checking of integer multipliers

    Publication Year: 2001, Page(s):169 - 174
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB) | HTML iconHTML

    In this paper, we address on equivalence checking of integer multipliers, especially for the multipliers without structure similarity. Our approach is based on Hamaguchi's backward substitution method with the following improvements: (1) automatic identification of components to form proper cut points and thus dramatically improve the backward substitution process; (2) a layered-backward substitut... View full abstract»

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