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Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871)

17-19 April 2000

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  • Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871)

    Publication Year: 2000
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    Freely Available from IEEE
  • Combining serialisation and reconfiguration for convolver designs

    Publication Year: 2000, Page(s):344 - 346
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (273 KB)

    This paper describes techniques for combining serialisation and reconfiguration to produce efficient convolver designs. Several optimisation techniques, such as restructuring and pipeline morphing, are presented with an analysis of their impact on performance and resource usage. The proposed techniques do not require the basic processing element to be modified. An estimate of the performance of a ... View full abstract»

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  • Author index

    Publication Year: 2000, Page(s):347 - 348
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    Freely Available from IEEE
  • Implementation of a configurable controller for an AC drive control: a case study

    Publication Year: 2000, Page(s):323 - 324
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB)

    There are several different approaches to defining reconfigurable systems. Reconfigurable computing is also often called Custom or Adaptive. The significant potential for the acceleration of computing in general-purpose applications has been demonstrated (S. Hauck, 1998; J. Villasnor and W.H. Mangionesmith, 1997). Reconfigurable systems are those computing platforms whose architecture is modified ... View full abstract»

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  • A scalable, loadable custom programmable logic device for solving Boolean satisfiability problems

    Publication Year: 2000, Page(s):13 - 21
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    This paper introduces ELVIS, a custom PLD that solves Boolean satisfiability (SAT) problems and presents a significant improvement over previous approaches. SAT is a core computer science problem with important commercial applications, which include timing verification, automated layout, logic minimization and test pattern generation. ELVIS is the first massively parallel SAT-solver to support eff... View full abstract»

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  • Accelerating embedded applications using dynamically reconfigurable hardware and evolutionary algorithms

    Publication Year: 2000, Page(s):321 - 322
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB)

    The authors propose an evolutionary algorithm (EA) approach to hardware-software partitioning and performance estimation of dynamically reconfigurable embedded systems. A demonstrative application is used to show the effectiveness of the use of GAs to achieve hardware-software partitions with maximum speedup View full abstract»

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  • BigSky - an on-line arithmetic design tool for FPGAs

    Publication Year: 2000, Page(s):303 - 304
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB)

    We present a project to design, implement and use online arithmetic (M.D. Ercegovac and T. Lang, 1988) modules for reconfigurable hardware suitable for signal processing tasks. The project involves: (i) design, implementation and evaluation of a library of parameterized macros for primitive and composite/variable precision arithmetic (Underground); (ii) development of a high-level design environme... View full abstract»

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  • Design of a VLIW compute accelerator on the Transmogrifier-2

    Publication Year: 2000, Page(s):3 - 12
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1084 KB)

    Design of FCCMs is an expensive and time consuming process, requiring a specialized software and hardware design for each application. A new class of architecture and compiler for customized computers called PECompiler that can automatically generate both hardware and software for field-programmable compute accelerators was recently introduced. This paper presents the parameterized compute acceler... View full abstract»

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  • Death of the RLOC?

    Publication Year: 2000, Page(s):145 - 152
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (800 KB)

    “RLOC” is the name given to a relational placement macro that is used to influence the layout of circuits that are realised on FPGAs using Xilinx's place and route software. This paper explores the thesis that modern FPGA architectures are powerful enough to no longer require the designer to provide a layout and that simulated annealing technology has advanced to the point that very go... View full abstract»

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  • A run-time reconfigurable plug-in for the Winamp MP3 player

    Publication Year: 2000, Page(s):319 - 320
    Cited by:  Papers (3)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    The paper describes a plug-in for the Winamp MP3 player that uses a configurable computer to provide digital special effects for audio streams. The plug-in makes use of run-time reconfiguration, modification of FPGA configuration bitstreams at run time, and context switching. The plug-in effects processor provides filters for a graphic equalizer and an echo effect. These filters are context-switch... View full abstract»

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  • Preemptive multitasking on FPGAs

    Publication Year: 2000, Page(s):301 - 302
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB)

    In exploring the efficacy of reconfigurable computing, one of the dimensions is the possibility for multitasking on an FPGA-based processor. Conventional computers and operating systems have demonstrated the many advantages of sharing computational hardware by several tasks over time. The ability to do run-time configuration and readback of FPGAs in a coprocessor architecture enables exploration o... View full abstract»

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  • An adaptive cryptographic engine for IPSec architectures

    Publication Year: 2000, Page(s):132 - 141
    Cited by:  Papers (18)  |  Patents (49)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (916 KB)

    Architectures that implement the Internet Protocol Security (IPSec) standard have to meet the enormous computing demands of cryptographic algorithms. In addition, IPSec architectures have to be flexible enough to adapt to diverse security parameters. This paper proposes an FPGA-based Adaptive Cryptographic Engine (ACE) for IPSec architectures. By taking advantage of FPGA technology, ACE can adapt ... View full abstract»

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  • FCCMs and the memory wall

    Publication Year: 2000, Page(s):329 - 330
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB)

    Although there has been considerable work in the conventional general purpose processors community on how to tackle an important looming problem, we are not aware of any similar effort for custom computing machines. The aim of this paper is to analyze the state of the art, pose the relevant questions, and indicate a preliminary solution vis a vis the following question: how will custom computing m... View full abstract»

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  • Configuration caching management techniques for reconfigurable computing

    Publication Year: 2000, Page(s):22 - 36
    Cited by:  Papers (35)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1132 KB)

    Although run-time reconfigurable systems have been shown to achieve very high performance, the speedups over traditional microprocessor systems are limited by the cost of configuration of the hardware. We explore the idea of configuration caching. We present techniques to carefully manage the configurations present on the reconfigurable hardware throughout program execution. Through the use of the... View full abstract»

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  • Multiple precision for resource minimization

    Publication Year: 2000, Page(s):307 - 308
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (156 KB)

    Presents the Synoptix high-level synthesis and precision optimization system for FPGAs. Given abstract specifications in the form of infinite-precision signal flow graphs and a set of error constraints, Synoptix creates hardware descriptions of fixed-point arithmetic implementations. The width of each signal is individually optimized in order to achieve the minimal resource utilization while satis... View full abstract»

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  • Dynamic fault tolerance in FPGAs via partial reconfiguration

    Publication Year: 2000, Page(s):165 - 174
    Cited by:  Papers (50)  |  Patents (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (972 KB)

    In this paper we present an on-line, multi-level fault tolerant (FT) technique for system functions and applications mapped to partially and dynamically reconfigurable FPGAs. Our method is based on the roving self testing areas (STARs) fault detection/location strategy presented in Abramovici et al. (1999). In STARs, the area under test uses partial reconfiguration properties to modify the configu... View full abstract»

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  • Stream-oriented FPGA computing in the Streams-C high level language

    Publication Year: 2000, Page(s):49 - 56
    Cited by:  Papers (86)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    Stream oriented processing is an important methodology used in FPGA-based parallel processing. Characteristics of stream-oriented computing include high-data-rate flow of one or more data sources; fixed size, small stream payload (one byte to one word); compute-intensive operations, usually low precision fixed point, on the data stream; access to small local memories holding coefficients and other... View full abstract»

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  • An FPGA-based array processor for an ionospheric-imaging radar

    Publication Year: 2000, Page(s):313 - 314
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    Atmospheric scientists need to observe fluctuations in the ionosphere, both to probe the underlying atmospheric physics and to remove the effects of these fluctuations from other measurements. We have built an FPGA-based, pipelined array processor that allows us to make these observations in real-time, using passive radar techniques. Our array processor time-multiplexes 16 multiply-accumulators ac... View full abstract»

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  • Interfacing reconfigurable logic with a CPU

    Publication Year: 2000, Page(s):317 - 318
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    Reconfigurable computing devices have achieved substantial performance improvements over conventional processors on some computational kernels. These benefits derive from hardware customization which avoids the mismatch between the basic requirements of the algorithms and the architectures of the processors. A reconfigurable fabric alone is not sufficient for general-purpose computing since it can... View full abstract»

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  • Reconfigurable array media processor (RAMP)

    Publication Year: 2000, Page(s):287 - 288
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB)

    This paper presents the architecture of a Reconfigurable Array Media Processor (RAMP). RAMP features a 2D array of coarse-grained configurable logic blocks (CLBs) connected together by local and global inter-connects. The CLBs on RAMP provide a 4-bit ALU, 2×2 bit parallel multiply function, 4-bit barrel shifter, two 4-bit registers and a local programmable control unit. RAMP is capable of pa... View full abstract»

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  • Mapping algorithms for a multi-bit data path processing reconfigurable chip RHW

    Publication Year: 2000, Page(s):281 - 282
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB)

    While FPGAs are mainly used for implementing general purpose logic circuits, the RHW works with the CPU to accelerate the computation intensive part of the application by reconfiguring its data paths and ALUs optimized for the algorithm. Hence the RRW was designed to implement multi-bit data paths and ALUs efficiently. We developed a new architecture that consists of a two-dimensional array of mul... View full abstract»

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  • Hardware accelerator for subgraph isomorphism problems

    Publication Year: 2000, Page(s):283 - 284
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB)

    Many applications can be modeled as subgraph isomorphism problems, which are generally NP-complete. This paper presents an algorithm that is suited for hardware implementation. The prototype accelerator that operates at 16.5 MHz on a Lucent ORCA 2C15A FPGA outperforms the software implementation of Ullmann's algorithm on a 400 MHz Pentium II by 10 times in the best case View full abstract»

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  • A communication scheduling algorithm for multi-FPGA systems

    Publication Year: 2000, Page(s):299 - 300
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    For multiple FPGA systems, the limited number of I/O pins causes many problems. To solve these problems, efficient communication scheduling among FPGAs is crucial for obtaining high CLB utilization. We provide a heuristic for the NP-complete scheduling algorithm. Experimental results show that our algorithm generates excellent communication schedules: more than 90% of the randomly generated proble... View full abstract»

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  • An investigation of reconfigurable multipliers for use in adaptive signal processing

    Publication Year: 2000, Page(s):341 - 343
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    This paper looks at various XC6200 multiplier architectures for use within adaptive signal processing systems. It compares data throughput, block utilisation and reconfiguration times. A number of approaches are compared including fully programmable multipliers and three separate ways of implementing reconfigurable multipliers. The paper shows how fixed coefficient multipliers can be used to incre... View full abstract»

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  • Improving the performance and efficiency of an adaptive amplification operation using configurable hardware

    Publication Year: 2000, Page(s):267 - 275
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (748 KB)

    An adaptive amplification operation has been designed and tested in configurable hardware for a computationally intensive object recognition system. This configurable system provides over forty-one times the throughput of an industry-standard embedded processor by exploiting the bandwidth of internal block memories and parallelism within the algorithm. Operating at less than one half the power of ... View full abstract»

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