By Topic

Test Conference, 2000. Proceedings. International

Date 3-5 Oct. 2000

Filter Results

Displaying Results 1 - 25 of 125
  • Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159)

    Save to Project icon | Request Permissions | PDF file iconPDF (635 KB)  
    Freely Available from IEEE
  • Author index

    Page(s): 1157 - 1158
    Save to Project icon | Request Permissions | PDF file iconPDF (166 KB)  
    Freely Available from IEEE
  • Universal test generation using fault tuples

    Page(s): 812 - 819
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (600 KB)  

    A test generation tool for combinational circuits called FATGEN has been developed based on the notion of fault tuples. FATGEN can be used to simultaneously generate tests for many types of misbehavior that occur in digital systems. Individual experiments involving SSL, transistor stuck-open, path delay and bridging faults for the ISCAS85 benchmark circuits reveal an average speedup of nearly 32% and test set compaction of 60% when faults of all types are analyzed simultaneously. In addition, there is an average reduction of approximately 34% in the number of aborted faults View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low power BIST design by hypergraph partitioning: methodology and architectures

    Page(s): 652 - 661
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1000 KB)  

    Power consumption of digital systems may increase significantly during testing. In this paper, we propose a novel low power/energy Built-in Self Test (BIST) strategy based on circuit partitioning. The strategy consists of partitioning the original circuit into structural subcircuits so that each subcircuit can be successively tested through different BIST sessions. In partitioning the circuit and planning the test session, the switching activity in a time interval (i.e. The average power) as well as the peak power consumption are minimized. Moreover, the total energy consumption during BIST is also reduced since the test length required to test the subcircuits is not so far from the test length for the original circuit. The proposed strategy can be applied to either test-per-scan or test-per-clock BIST schemes by slightly modifying conventional TPG structures as illustrated in this paper. Results on ISCAS circuits show that average power reduction of up to 62%, peak power reduction of up to 57%, and energy reduction of up to 82% can be achieved at a very low area cost in terms of area overhead and with almost no penalty on the circuit timing View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Concurrent error detection in block ciphers

    Page(s): 979 - 984
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (468 KB)  

    Today, encryption is widely used to incorporate privacy in data communications. Hardware implementations of encryption algorithms are fast enough to cope with the high throughput required in modern transmission channels. However, faults may occur in such circuits that can cause errors in encrypted text. A new technique is proposed to concurrently detect errors in block ciphers. It introduces very low area overhead in the system. In addition, a new encoding scheme is presented that has higher detection capabilities than other common error detection codes, when applied to encryption systems. Experiments conducted with widely used encryption algorithms (DES, RC5, IDEA and SKIPJACK) demonstrate the advantages of the proposed technique View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Deterministic partitioning techniques for fault diagnosis in scan-based BIST

    Page(s): 273 - 282
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (840 KB)  

    A deterministic partitioning technique for fault diagnosis in scan-based BIST is proposed. Properties of high quality partitions for improved fault diagnosis times are identified and low cost hardware implementations of high quality deterministic partitions are outlined. The superiority of the partitions generated by the proposed approach is confirmed through mathematical analysis. Theoretical analyses, worst case bounds, and experimental simulation data all confirm the superiority of the proposed deterministic approaches View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Challenges of high supply currents during VLSI test

    Page(s): 1013 - 1020
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (700 KB)  

    Very high power supply currents required during test of advanced VLSI parts pose problems for both the ATE power supply and the interconnect to the DUT. Power supply design, inductance, resistance, filter capacitance and sense points all become critical. Design of the DUT interface board requires careful attention to detail View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A mixed mode BIST scheme based on reseeding of folding counters

    Page(s): 778 - 784
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB)  

    In this paper a new scheme for deterministic and mixed mode scan-based BIST is presented. It relies on a new type of test pattern generator which resembles a programmable Johnson counter and is called folding counter. Both the theoretical background and practical algorithms are presented to characterize a set of deterministic test cubes by a reasonably small number of seeds for a folding counter. Combined with classical approaches for test width compression and with pseudorandom pattern generation these new techniques provide an efficient and flexible solution for scan-based BIST. Experimental results show that the proposed scheme outperforms previously published approaches based on the reseeding of LFSRs or Johnson counters View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Doing it in STIL: intelligent conversion from STIL to an ATE format

    Page(s): 64 - 71
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (588 KB)  

    The STIL test language has recently become a standard. Most test systems do not use STIL as a native language, however. There is a requirement for conversion from STIL to a tester's native language. This paper presents a methodology for intelligent and efficient conversion from STIL to a cycle-based tester format View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A BIST approach for very deep sub-micron (VDSM) defects

    Page(s): 283 - 291
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (548 KB)  

    This paper presents a BIST approach for the very deep submicron (VDSM) defects in an ASIC. As bridging or open defects are dominant in VDSM, efficient and accurate tests to detect them are now strongly required. We evaluated the BIST patterns for various criteria. These evaluations and additional real chip experiments have indicated that BIST has better detectability of defects than the conventional stored test View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Identification of crosstalk switch failures in domino CMOS circuits

    Page(s): 502 - 509
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (592 KB)  

    Capacitative coupling will become a dominant problem due to increased parasitic capacitance between adjacent wires and faster signal switching rates. The coupling problem is more acute for domino logic circuits since an irreversible gate output transition can result. We present a method to analyze domino circuits for susceptibility to crosstalk failures from a layout-extracted netlist. Specifically, sites in the circuit that may fail due to crosstalk are identified. In addition, failure sites are partitioned into two categories (faults or design errors) based on their likelihood of occurrence in the context of manufacturing variations. The method has been implemented and applied to a dual-rail domino Wallace tree circuit with little loss in accuracy, resulting in a 37X speedup over a full analysis using Hspice View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique

    Page(s): 971 - 978
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (616 KB)  

    Re-computing with shifted operands (RESO) is a logic level time redundancy based concurrent error detection (CED) technique. In RESO, logic level operations (and, nand, etc) are carried out twice-once on the basic input and once on the shifted input. Results from these two operations are compared to detect an error. Although using RESO operators in register transfer level (RTL) designs is straightforward, it entails time and area overhead. We developed an RTL CED technique called algorithm level re-computing with shifted operands (ARESO). ARESO does not use specialized RESO operators. Rather, it exploits RTL scheduling, pipelining, operator chaining, and multi-cycling to incorporate user specified error detection latencies. ARESO supports hardware vs. performance vs. error detection latency trade-offs. ARESO has been validated on practical design examples using Synopsys Behavior Compiler View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Test generation for path-delay faults in one-dimensional iterative logic arrays

    Page(s): 326 - 335
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (860 KB)  

    We propose a test generation method for path-delay faults in combinational iterative logic arrays (ILAs). The number of paths as well as the number of critical paths in ILAs can grow exponentially with the number of stages. Existing path-delay test generation techniques explicitly target each selected path and cannot generate tests for ILAs with reasonable numbers of stages, e.g., 16 and 32. The proposed method overcomes this difficulty by implicitly targeting all testable paths and can generate tests for ILAs of arbitrary size and guarantees coverage of all testable faults. The proposed method also drastically decreases the test data volume to be stored in the high-speed memories in the probe unit of the tester by generating tests in the form of a small number of expressions. This is of great benefit since the ability to store large volumes of test data is a significantly greater limiting factor than the time required to apply the tests. Finally, for most ILAs, this method produces a compact set of tests View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Test program synthesis for path delay faults in microprocessor cores

    Page(s): 1080 - 1089
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (852 KB)  

    This paper addresses the problem of testing path delay faults in a microprocessor core using its instruction set. We propose to self-test a processor core by running an automatically synthesized test program which can achieve a high path delay fault coverage. This paper discusses the method and the prototype software framework for synthesizing such a test program. Based on the processor's instruction set architecture, micro-architecture, RTL netlist as well as gate-level netlist on which the path delay faults are modeled, the method generates deterministic tests (in the form of instruction sequences) by cleverly combining structural and instruction-level test generation techniques. The experimental results for two microprocessors indicate that the test instruction sequences can be successfully generated for a high percentage of testable path delay faults View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • HD2BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs

    Page(s): 892 - 901
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (788 KB)  

    Proposes HD2BIST, a complete hierarchical framework for BIST scheduling, data patterns delivering, and diagnosis of a complex system including embedded cores with different test requirements as full scan cores, partial scan cores, or BIST-ready cores. The main goal of HD 2BIST is to maximize and simplify the reuse of the built-in test architectures, giving the chip designer the highest flexibility in planning the overall SoC test strategy. HD2BIST defines a test access method able to provide a direct “virtual” access to each core of the system, and can be conceptually considered as a powerful complement to the P1500 standard, whose main target is to make the test interface of each core independent from the vendor View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multiple-parameter CMOS IC testing with increased sensitivity for I DDQ

    Page(s): 1051 - 1059
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (740 KB)  

    Technology scaling challenges the effectiveness of current-based test techniques such as IDDQ. Furthermore, existing leakage reduction techniques are not as effective in aggressively scaled technologies. We exploited intrinsic dependencies of transistor and circuit leakage on clock frequency, temperature, and reverse body bias (RBB) to discriminate fast ICs from defective ones. Transistor and circuit parameters were measured and correlated to demonstrate leakage-based testing solutions with improved sensitivity. We used a test IC with available body terminals for our experimental measurements. Our data suggest adopting a sensitive multiple-parameter test solution. For high performance IC applications, we propose a new test technique, I DDQ versus FMAX (maximum operating frequency), in conjunction with using temperature (or RBB) to improve the defect detection sensitivity. For cost sensitive applications, IDDQ versus temperature test can be deployed. Our data show that temperature (cooling from 110°C to room) improved sensitivity of IDDQ Versus FMAX two-parameter test by more than an order of magnitude (13.8X). The sensitivity can also be tuned by proper selection of a temperature range to match a required DPM level View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On-line and off-line test of airborne digital systems: a reliability study

    Page(s): 35 - 44
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (656 KB)  

    This paper deals with studying the effects of both on-line and off-line test during flight critical missions where safety is a major issue. The on-line test, in this context, is a test performed on a digital airborne system during some specified windows in time while it is still performing its intended task. An off-line test is a test that is performed on the digital system once it is taken, off-line because of a suspected failure. Both the on-line and the off-line tests are performed during flight. The difference between the two is that the off-line test can be made more effective than an on-line test due to the longer amount of time available for testing. Moreover, the off-line test may be designed to have diagnosis and repair capabilities built-in. Upon successful repair, the faulty processor may be reconfigured back into the system. This capability will undoubtedly increase the mission reliability View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An empirical study on the effects of test type ordering on overall test efficiency

    Page(s): 408 - 416
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (720 KB)  

    The order in which the various test types are applied can have an impact on the overall efficiency of the test operation. Furthermore, the speed at which the tests can be executed and the latency of defect detection are also important factors. In this paper, we evaluate an exhaustive set of test orderings over a variety of assumed execution parameters to analyze their effects on overall tester time consumption View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Computer-aided fault to defect mapping (CAFDM) for defect diagnosis

    Page(s): 729 - 738
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1128 KB)  

    Defect diagnosis in random logic is currently done using the stuck-at fault model, while most defects seen in manufacturing result in bridging faults. In this work we use physical design and test failure information combined with bridging and stuck-at fault models to localize defects in random logic. We term this approach computer-aided fault to defect mapping (CAFDM). We build on top of the existing mature stuck-at diagnosis infrastructure. The performance of the CAFDM software was tested by injecting bridging faults into samples of a Streaming audio controller chip and comparing the predicted defect locations and layers with the actual values. The correct defect location and layer was predicted in all 9 samples for which scan-based diagnosis could be performed. The experiment was repeated on production samples that failed scan test, with promising results View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Digital signature proposal for mixed-signal circuits

    Page(s): 1041 - 1050
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    A new BIST structure, based on the information provided by the XY-operation (Lissajous curves) is introduced in this paper. A digital signature is obtained which is used to discriminate catastrophic as well as parametric defects. High fault coverage is achieved when applying the proposed BIST on an ITC'97 benchmark circuit where 92% of the catastrophic defects and 87.5% of the parametric defects analyzed produced digital signatures clearly distinguishable from the golden signature View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • DIST-based detection and diagnosis of multiple faults in FPGAs

    Page(s): 785 - 794
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (916 KB)  

    We present a BIST-based approach able to detect and accurately diagnose any single and most multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs). For any faulty PLB, we also identify its internal faulty modules or modes of operation. This accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Successful implementation of structured testing

    Page(s): 344 - 348
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    This paper describes techniques developed to successfully implement structured testing into the manufacturing flow. Analysis and discussion of the main techniques will be presented to show how these techniques are optimized through systematic learning View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Power conscious test synthesis and scheduling for BIST RTL data paths

    Page(s): 662 - 671
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (840 KB)  

    Previous research has outlined that power dissipated during test application is substantially higher than during functional operation, which leads to loss of yield and decreases reliability. This paper shows for the first time how power is minimized in BIST RTL data paths by using power conscious test synthesis and test scheduling. According to the necessity for achieving the required test efficiency, power dissipation is classified into necessary and useless power dissipation. According to the occurrence during the testing process, power dissipation is classified into test application and shifting power dissipation. The effect of test synthesis and scheduling on power dissipation is analyzed and power minimization is achieved in two steps. Firstly, during the testable design space exploration only power conscious test synthesis moves are accepted leading to minimization of useless power dissipation. Secondly, module selection during power conscious test scheduling satisfies power constraints while reducing test application time. Experimental results using generic power models show savings up to 28% in test application power dissipation and up to 29% in shifting power dissipation View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Easy mixed signal test creation with test elements and procedures

    Page(s): 72 - 79
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB)  

    A test engineer who creates complex mixed-signal tests by grouping graphical test elements into custom test procedures combines the ease-of-use of GUI-based template programming with the flexibility and power of a code-based approach View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Combinational logic synthesis for diversity in duplex systems

    Page(s): 179 - 188
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (840 KB)  

    We describe logic synthesis techniques for designing diverse implementations of combinational logic circuits in order to maximize the data integrity of diverse duplex systems in the presence of common-mode failures. Data integrity means that the system either produces correct outputs or indicates errors when incorrect outputs we produced. Design diversity has long been used to increase the data integrity of duplex systems against common-mode failures. The conventional notion of diversity is qualitative and relies on “independent” generation of “different” implementations. In a recent paper, we presented a metric to quantify, diversity among several designs. Our synthesis techniques described in this paper use the diversity metric as a cost function and maximize diversity while reducing the area overhead of the resulting diverse duplex system View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.