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# 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125)

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Displaying Results 1 - 25 of 72
• ### 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125)

Publication Year: 2000
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• ### A 0.5-1 V MTCMOS/SIMOX SRAM macro with multi-V/sub th/ memory cells

Publication Year: 2000, Page(s):24 - 25
Cited by:  Papers (5)
| | PDF (164 KB)

Summary form only given. Sub-1 V CMOS circuit technology on ultrathin-film SOI is the most effective candidate for ultralow-power applications in future ULSIs. We have proposed various multi-threshold CMOS/SIMOX (MTCMOS/SIMOX) circuits (Douseki et al., 1996; Fujii et al., 1998) that operate at an ultralow supply voltage down to 0.5 V. Combining fully-depleted low-V/sub th/ CMOS logic gates and par... View full abstract»

• ### 2-D imaging of trapped charge in SiO/sub 2/ using scanning Kelvin probe microscopy

Publication Year: 2000, Page(s):38 - 39
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Summary form only given. TCAD has recently been gaining attention as a tool for the design of radiation hard ICs. Milanowski et al (1998) demonstrated how TCAD simulations could be used to predict edge-enhanced buried oxide hole trapping and its impact on back channel leakage in SOI MOSFETs. The accuracy of TCAD depends strongly on the accuracy of the underlying models of the density and distribut... View full abstract»

• ### Author index

Publication Year: 2000, Page(s):144 - 145
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• ### Photoluminescence analysis of annealing process in low-dose SIMOX wafers

Publication Year: 2000, Page(s):44 - 45
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A thin film silicon-on-insulator (SOI) wafer synthesized by separation by implantation of oxygen (SIMOX) is regarded as one of the most promising substrates for the next-generation low-power, high-speed, and highly integrated devices. Low-dose SIMOX in particular has the advantages of low defect density and low production cost. The method requires high-temperature annealing not only to eliminate i... View full abstract»

• ### Average transient current in SOI MOSFETs: a new technique for measuring the transient floating body effects

Publication Year: 2000, Page(s):64 - 65
Cited by:  Papers (2)
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Several studies have demonstrated that floating body effects in partially-depleted SOI-CMOS technology can have a beneficial impact on the performance of digital circuits (Cristoloveanu and Li, 1995; Gautier et al., 1997). Nevertheless, the electrical characterization of transient phenomena is a difficult problem because the associated time constants can be close to a few nanoseconds. Direct measu... View full abstract»

• ### A real time infrared scene simulator in CMOS/SOI MEMS

Publication Year: 2000, Page(s):42 - 43
Cited by:  Papers (3)
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A 64×128 real-time infrared (RTIR) CMOS/SOI scene generation IC is presented. The RTIR IC offers real-time dynamic thermal scene generation. This system is a mixed mode design, with analog scene information written and stored into a thermal pixel array. The design presented utilizes micro-electromechanical systems (MEMS) in conjunction with the 0.8 μm SPAWAR CMOS/SOI process to develop a ... View full abstract»

• ### Surface finishing of cleaved SOI films using epi technologies

Publication Year: 2000, Page(s):12 - 13
Cited by:  Papers (3)  |  Patents (4)
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The use of epi technologies in SOI manufacturing is shown to add flexibility and increased wafer quality, e.g. fewer defects and better top Si-layer uniformity, as well as cluster-tool compatibility. The newly developed smoothing process on the Epi Centura replaces touch-polishing after bond and cleave. RMS values down to 0.08 nm have been achieved on wafers with an initial RMS value as high as 8 ... View full abstract»

• ### 850 V DMOS-switch in silicon on-insulator with specific Ron of 13 Ω-mm2

Publication Year: 2000, Page(s):62 - 63
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A 13 mask, double metal process is presented for high-voltage applications. Double RESURF in the silicon-on-insulator layer permits realization of 850 V devices on less than half the surface area of corresponding devices in bulk silicon View full abstract»

• ### “Gated diode” characterization of hot carrier induced interface state and oxide charge lateral profiles in SOI MOSFET's

Publication Year: 2000, Page(s):40 - 41
| | PDF (112 KB)

The quality and the degradation (induced by hot carriers, irradiation, etc.) of the Si-SiO2 interfaces remains an important issue in the development of SOI CMOS technologies, and continues to be difficult to measure and characterize. We previously described (Zhao and Ioannou, 1999) a “gated-diode” (Speckbacher et al, 1995; Okhonin et al, 1996) based approach to measure the i... View full abstract»

• ### Modeling and fabrication of vertical pillar MOSFETs made in recrystallized Si

Publication Year: 2000, Page(s):50 - 51
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We report a simple analytical model for vertical pillar MOSFETs including bulk traps. The model predicts that the threshold voltage increases as the trap density increases. The analytical solution yields good agreement with MEDICI simulations confirming the model. The model is used to evaluate the electrical characteristics of devices previously fabricated (Cho et al, Symp. VLSI Tech., p. 31, 1999... View full abstract»

• ### Scalability potential in ELTRAN(R) SOI-epi wafer

Publication Year: 2000, Page(s):10 - 11
Cited by:  Papers (5)  |  Patents (1)
| | PDF (116 KB)

For coming device applications, advanced requirements for silicon-on-insulator (SOI) wafers are increasing. One of the most important items is scalability that includes scaling up of the wafer diameter and scaling down of the SOI layer thickness (tSOI). 300 mm wafers and ultra thin SOI with tSOI less than 100 nm will be required according to the ITRS (SIA, 1999). 300 mm SOI w... View full abstract»

• ### Characterization of the parasitic bipolar transistor in SOI technology: comparison between direct and indirect triggering techniques

Publication Year: 2000, Page(s):86 - 87
Cited by:  Papers (8)
| | PDF (128 KB)

Soft error FIT (failure in time) requirements is an increasing challenge for high performance CMOS applications. Projections show that a 100 times increase in sensitivity is expected for the technologies produced in the next decade (Cohen et al, 1999). To reduce the sensitivity of ICs, different approaches have been tried such as the implementation of a circuit based solution to protect the memory... View full abstract»

• ### Analysis and suppression of hysteretic behaviors in PD-SOI CMOS circuits

Publication Year: 2000, Page(s):60 - 61
Cited by:  Papers (1)
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Recent advances in ultra-thin silicon-on-insulator (SOI) technology have made partially depleted (PD)-SOI-CMOS a promising candidate for use in high-speed circuits. However, some breakthroughs must still be made, the most important of which would be understanding and control of hysteretic behavior. Some hysteretic characteristics have been analyzed, and some methods to suppress this behavior have ... View full abstract»

• ### Architecture of SOI transistors: what's next?

Publication Year: 2000, Page(s):1 - 2
Cited by:  Papers (1)
| | PDF (136 KB)

The long but successful efforts of the silicon-on-insulator (SOI) community have eventually put SOI in the microelectronics roadmap. It is frequently stated that SOI is capable of expanding the predictable frontiers of bulk-silicon technology. It is even speculated that SOI transistors will be the unique survivors of the CMOS world. For this promise to materialize, both evolutionary' and revolut... View full abstract»

• ### Smart card circuits in SOI technology

Publication Year: 2000, Page(s):48 - 49
Cited by:  Papers (1)  |  Patents (2)
| | PDF (100 KB)

Smart cards have recently evolved towards very complex systems-on-a-chip, thereby opening new opportunities and creating new demands on fabrication technologies for higher integration density as well as lower power, lower voltage operation. In this work, we investigated the feasibility of realizing the blocks of a smart card chip in SOI technology. In the first part of the paper, we discuss the po... View full abstract»

• ### High performance 0.1 μm partially depleted SOI CMOSFET

Publication Year: 2000, Page(s):68 - 69
| | PDF (148 KB)

The partially depleted SOI MOSFET (PD-SOI) has been found to be an attractive device due to advantages such as full dielectric isolation and reduced junction capacitance compared to the bulk Si device (Assaderaghi et al, 1997; Maeda et al, 2000). However, the floating body effect occurs on PD-SOI devices, resulting in threshold voltage reduction and noise overshoot (Tseng et al, 1997). Body contac... View full abstract»

• ### An impact of GIDL off leakage on low-power sub-0.2 μm SOI CMOS applications

Publication Year: 2000, Page(s):90 - 91
| | PDF (104 KB)

The speed advantage of SOI CMOSFETs has exclusively been claimed for front-end applications (Ajmera et al, 1999), but its potential for low-power applications has rarely been discussed. Recently, it was reported that BF (body floating)-enhanced short-channel effects increase Vt-limited off leakage, for which Vt must be larger than bulk CMOS, thus resulting in no performance m... View full abstract»

• ### SOI at IBM: current status of technology, modeling, design, and the outlook for the 0.1 μm generation

Publication Year: 2000, Page(s):6 - 9
Cited by:  Papers (6)
| | PDF (292 KB)

This paper reviews the evolution of partially depleted (PD) CMOS SOI technology at IBM. Several aspects of this development leading to successful fabrication of high-performance microprocessors are discussed. They include SOI-specific device design and process modifications; creation of compact device models for circuit simulation (SPICE-like models); and development of circuit styles and strategi... View full abstract»

• ### Co salicide technology for sub-0.15 μm FD-SOI and beyond: super-flat silicide and fully-silicided source/drain structure

Publication Year: 2000, Page(s):72 - 73
Cited by:  Papers (1)  |  Patents (1)
| | PDF (128 KB)

Fully-depleted SOI devices have excellent characteristics for low power applications, in such regards as low subthreshold swing, low source/drain (S/D) capacitance and small floating body effect compared to bulk devices or partially-depleted SOI devices (Imai et al, 1998; Chen et al, 1999). These features derive from the thin SOI layer whose typical thickness is less than 50 nm; however, silicidat... View full abstract»

• ### Comparative analysis of PD-SOI active body-biasing circuits

Publication Year: 2000, Page(s):94 - 95
Cited by:  Papers (5)  |  Patents (16)
| | PDF (120 KB)

The body of SOI partially depleted MOSFETs can be biased to control the threshold dynamically. In the dynamic threshold MOSFET (DTMOS) (Assaderaghi et al, 1997), the operation is limited to about V dd=0.7 V because of the forward bias of the B-D and B-S junctions. Active body-biasing circuits (ABC-SOI) use auxiliary transistors to implement the bias circuitry and to increase the Vd... View full abstract»

• ### A novel compact model of quantum effects in scaled SOI and double-gate MOSFETs

Publication Year: 2000, Page(s):114 - 115
Cited by:  Papers (1)
| | PDF (144 KB)

Quantum-mechanical (QM) confinement of inversion-layer carriers significantly affects the threshold voltage and gate capacitance of highly scaled MOSFETs. In bulk-Si and partially depleted (PD) SOI (n)MOSFETs, the confinement is in the potential well defined by the gate-oxide barrier (which is virtually infinite) and the silicon conduction (or valence) band (the steep gradient of which defines the... View full abstract»

• ### SOI wafer selection for CCD/SOI-CMOS technology

Publication Year: 2000, Page(s):136 - 137
Cited by:  Papers (1)  |  Patents (1)
| | PDF (156 KB)

We have developed a process that monolithically integrates fully depleted SOI CMOS (FDSOI) with high-performance CCD image sensors (Suntharalingam et al, 2000). This integrated technology enables charge-coupled devices (CCDs) to be in close proximity to, yet isolated from, FDSOI circuits. This approach exploits both the advantages of FDSOI (fast, low-power CMOS with potentially enhanced radiation ... View full abstract»

• ### Ratioed CMOS: a low power high speed design choice in SOI technologies

Publication Year: 2000, Page(s):28 - 29
Cited by:  Papers (4)
| | PDF (156 KB)

Ratioed CMOS gates implemented in a partially-depleted (PD) SOI CMOS technology are usually considered to be high power but end up being both faster and lower power than other circuit implementations, mainly due to the reduced junction capacitance in SOI devices as well as floating-body effects. As an example, a high performance multiplier shifter is 3 to 4 times faster and dissipates 9 times less... View full abstract»

• ### Back gate engineering for suppression of threshold voltage fluctuation in fully-depleted SOI MOSFETs

Publication Year: 2000, Page(s):78 - 79
| | PDF (144 KB)

Threshold voltage fluctuation due to SOI thickness variation is one of the most serious problems in fully-depleted (FD) SOI MOSFETs. In order to suppress this threshold voltage (Vth) fluctuation in FD SOI-MOSFETs, we propose a new back gate engineering scenario in which the back gate is biased in order to make the back interface of SOI films weakly accumulated, under very thin buried ox... View full abstract»