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Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on

Date 25-27 Oct. 2000

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Displaying Results 1 - 25 of 47
  • Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

    Publication Year: 2000
    Request permission for commercial reuse | PDF file iconPDF (216 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 2000, Page(s):421 - 422
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    Freely Available from IEEE
  • A new defect outline model used for critical area estimation in VLSI

    Publication Year: 2000, Page(s):21 - 29
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    The calculation of critical area is the main computational problem in yield estimation of VLSI. For efficient critical area calculation, it is usually assumed that defects related to photolithography all have the shape of a circular disc and only the diameter of the disc is used to characterize the size of an actual defect. The actual critical area of a real defect, however, is determined by its d... View full abstract»

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  • IC critical volume calculation through ray-casting of CSG trees

    Publication Year: 2000, Page(s):12 - 20
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    This paper describes a method of finding the critical volume of integrated circuit (IC) layers. The aim of the technique is to calculate metrics of an IC that can be used to estimate the chip yield. The layout itself and the defects that arise in production are considered to be three-dimensional, as opposed to two-dimensional, objects View full abstract»

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  • The effect of placement on yield for standard cell designs

    Publication Year: 2000, Page(s):3 - 11
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    The ability to improve the yield of integrated circuits through layout modification has been recognized and several techniques for yield enhanced routing and compaction have been developed. Yield improvement during routing is however, limited by the predetermined placement. It is conceivable therefore, that different placements of the modules (e.g., standard or custom cells) may lead to very diffe... View full abstract»

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  • Optimization of wafer scale H-tree clock distribution network based on a new statistical skew model

    Publication Year: 2000, Page(s):96 - 104
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    Available statistical skew model is too conservative to estimate the expected clock skew of a well-balanced H-tree. New closed form model is presented for accurately estimating the expected values and the variances of both clock skew and the largest clock delay of a well-balanced H-tree. Based on the new model, clock period optimization of wafer scale H-tree clock network is investigated under two... View full abstract»

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  • A new light-based logic IC screening method

    Publication Year: 2000, Page(s):358 - 366
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    This paper describes a new screening method to combine Idd leakage current testing with light exposure on the surface of CMOS logic chips. The relationship between light and Idd leakage current is well known, and this new screening method makes use of the relationship. The Idd leakage current is tested both with and without light on the surface of the device under... View full abstract»

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  • Design of a fault tolerant multistage interconnection network with parallel duplicated switches

    Publication Year: 2000, Page(s):143 - 151
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    In this paper we propose a fault tolerant baseline network as a sort of MINs (multistage interconnection networks) and discuss its performance analysis. For our MIN with N input and N output terminals, switching elements in the first and n-th stages are duplicated where n=log2N. Four-input two-output switching elements and two-input four output ones employed in the second and (n-1)-th s... View full abstract»

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  • A reconfigurable WSI massively data-parallel processing device for cost-effective 3D sensor data processing

    Publication Year: 2000, Page(s):87 - 95
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    A performance-scalable ISDP (Interactive Sensor Data Processing) workstation, accelerated with commercial PCI multiprocessor cards, is described and a WSI massively data-parallel processor (MdPP) device is proposed for the replacement of its VLSI processors. Delivering 60 GOPS for 16-bit integer multiply-accumulate operations, a WSI-FPGA implementation of the reconfigurable device is shown to be b... View full abstract»

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  • Threshold voltage and power-supply tolerance of CMOS logic design families

    Publication Year: 2000, Page(s):349 - 357
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    The advent of deep submicron technologies brings new challenges to digital circuit design. A reduced threshold voltage (VT) and power supply (Vdd) in addition to process variabilities have a direct impact on circuit design. In a semiconductor environment it is conventionally thought that parametric yield is high and stable and that the main yield losses are functional. Althou... View full abstract»

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  • Design of switching blocks tolerating defects/faults in FPGA interconnection resources

    Publication Year: 2000, Page(s):134 - 142
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    Field programmable gate array is mainly composed of the interconnection resources area. Related defects/faults are therefore more probable than defects/faults in other regions of the chip. In this paper we propose a new approach tolerating defects/faults in interconnection resources. This approach is based on the modification of the switching block structure so that defects/faults could be avoided... View full abstract»

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  • Built-in self-reconfiguring systems for mesh-connected processor arrays with spares on two rows/columns

    Publication Year: 2000, Page(s):213 - 221
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    The author discusses some reconfiguration methods where faulty PEs are compensated for by spare PEs located in two rows/columns in/around a mesh-connected array since they have the advantages that the numbers of spare PEs and the network overheads for reconstructions are relatively small. First, the author discusses how arrangements of spare PEs and network architectures affect the efficiencies of... View full abstract»

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  • Self-configuration of a large area integrated multiprocessor system for video applications

    Publication Year: 2000, Page(s):78 - 86
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    We present a configuration technique for a Large Area Integrated Circuit (LAIC) which is manufactured by wafer stepping. A LAIC consists of four identical subsystems, i.e., a subsystem is the only building block of a LAIC and contains base cells or processing nodes as well as interconnects and pad cells. To ensure a proper cooperation of all subsystems and to enable communication between the subsy... View full abstract»

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  • Fault-tolerant high-performance CORDIC processors

    Publication Year: 2000, Page(s):164 - 172
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    This paper presents a low-cost approach to concurrent error detection in a high-performance CORDIC processor based on a conditional-sum scheme. The specific characteristics of the CORDIC computation and the processor allow fault detection at a low increase in circuit complexity and latency. The detection scheme is based on use of the AN codes for the arithmetic part and on duplication of the rotat... View full abstract»

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  • Using run-time reconfiguration for fault injection in hardware prototypes

    Publication Year: 2000, Page(s):405 - 413
    Cited by:  Papers (47)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    In this paper, approaches using run-time reconfiguration (RTR) for fault injection in programmable systems are introduced. In FPGA-based systems an important characteristic is the time to reconfigure the hardware. With novel FPGA families (e.g. Virtex, AT6000) it is possible to reconfigure the hardware partially in run-time. Important time-savings can be achieved when taking advantage of this char... View full abstract»

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  • Path delay fault testability analysis

    Publication Year: 2000, Page(s):338 - 346
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    The paper deals with the problem of testing delay path faults. We present results obtained with a newly developed test pattern generator. This generator is based on the use of reduced ordered binary decision diagrams (ROBDDs) and reveals many advantages as compared with other ATPGs published in the literature. An important contribution of the paper is the analysis of various testability features o... View full abstract»

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  • BIST architectures selection based on behavioral testing

    Publication Year: 2000, Page(s):292 - 298
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    BIST techniques have been widely explored to create the best performing self-testing architecture. Their success depends on the type of test pattern required by the circuit under test. The main goal of the paper is to show a methodology, based on behavioral information, to identify the best suited BIST architecture for a given circuit under test. LFSR-based architectures for behavioral test sequen... View full abstract»

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  • Quality-effective repair of multichip module systems

    Publication Year: 2000, Page(s):47 - 55
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    This paper proposes a new analytical approach for evaluating the effects of a repair process on the defect level of multichip module (MCM) systems at assembly. Repair of MCMs is usually required to improve the yield and quality of these systems, while preserving cost effectiveness. In the proposed approach, we develop a novel quality model, which is solved analytically in O(rN3) (where ... View full abstract»

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  • On the complexity of switch programming in fault-tolerant configurable chips

    Publication Year: 2000, Page(s):125 - 133
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    Given a programmable chip (such as a WSI systolic array, or a field programmable gate array (FPGA)) made of equally-like configurable logic blocks (cells), the problem of programming the interconnect resources (consisting of switches) has been well studied in the literature. This process can be used for fault tolerance by logically reconfiguring the fault free cells of the array into a new array a... View full abstract»

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  • “BOND”: An interposition agents based fault injector for Windows NT

    Publication Year: 2000, Page(s):387 - 395
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    The goal of this paper is to present BOND, a Software Fault Injection tool able to simulate abnormal behavior of a computer system running Windows NT 4.0 Operating System. The Fault Injector is based on interposition techniques, which guarantees a low impact on the execution of the target program, and allows the injection of Commercial off-the-Shelf software programs. BOND allows performing both s... View full abstract»

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  • Design for testability to achieve high test coverage. A case study

    Publication Year: 2000, Page(s):320 - 328
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    With the advent of the System-On-a-Chip (SoC) and mass production of these complex ICs, the design of an ASIC with testability features in it has become a mandatory requirement. Testability requirements are present in various levels of an SoC. The internal gates of the chip should be made testable for stuck-at faults. Internal hard-macros need to be tested for manufacturing defects. The connection... View full abstract»

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  • An on-line reconfigurable FPGA architecture

    Publication Year: 2000, Page(s):275 - 280
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB)

    FPGAs are widely used for prototyping of digital systems. A major problem of current FPGA architectures is that if there is a fault in a single combinational logic block (CLB), it may take a significant amount of time to find an alternative mapping of the circuit to bypass the faulty block. Thus, there is a need for new type of FPGA architecture that allows rapid recovery from internal faults in a... View full abstract»

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  • How does resource utilization affect fault tolerance?

    Publication Year: 2000, Page(s):251 - 256
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Many fault-tolerant architectures are based on the single-fault assumption, hence accumulation of dormant faults represents a potential reliability hazard. Based on the example of the fail-silent “Time-Triggered Architecture” we study sources and effects of dormant faults. We identify software as being more prone to dormant faults than hardware. By means of modeling we reveal a high se... View full abstract»

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  • Efficient error correction code configurations for quasi-nonvolatile data retention by DRAMs

    Publication Year: 2000, Page(s):201 - 209
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    This paper presents analyses of various configurations of error correction codes for the purpose of reducing the parity area for quasi-nonvolatile data retention by DRAMs. By combining long and short error correction codes, we show that the parity area can be reduced to less than 1% of the total memory size, yet the system can offer comparable reliability and adaptability as an earlier design that... View full abstract»

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  • A high speed and high fault tolerant reconfigurable reasoning system: toward a wafer scale reconfigurable reasoning LSI

    Publication Year: 2000, Page(s):69 - 77
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    A data direct implementation (DDI) technique for reasoning hardware using a large area FPGA or a wafer scale FPGA is proposed. In the DDI design methodology, the features in the past case data are extracted and converted to the truth tables using a genetic algorithm, and the truth tables (evolved truth tables) are synthesized to the logic circuits. Whereas the DDI requires reconfigurability in the... View full abstract»

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