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2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528)

11-13 Oct. 2000

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  • 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528)

    Publication Year: 2000
    Request permission for commercial reuse | PDF file iconPDF (316 KB)
    Freely Available from IEEE
  • Switched-adaptive interframe vector prediction with binary-tree searched predictors

    Publication Year: 2000, Page(s):733 - 742
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (515 KB)

    An approach for reducing the complexity of the switched-adaptive interframe vector prediction (SIVP) that is used for coding speech spectrum envelopes is proposed in this paper. To facilitate the search through the set of switched predictors used for prediction of the input LSF (line spectral frequency) vector, the predictors are organized in a binary tree structure. For a conventional full-search... View full abstract»

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  • Real time implementation of MPEG-1 Layer III audio decoder with TMS320C6201 DSP

    Publication Year: 2000, Page(s):761 - 770
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (510 KB)

    The goal of this research is the real-time implementation of an MPEG-1 Layer III audio decoder using the TMS320C6201 fixed-point digital signal processor (DSP). The main jobs for this work are twofold: one is to convert the floating-point operation in the decoder into a fixed-point operation while maintaining high resolution, and the other is to optimize the program to make it run in real time wit... View full abstract»

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  • Author index

    Publication Year: 2000, Page(s):0_2 - 0_4
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    Freely Available from IEEE
  • Precision for 2-D discrete wavelet transform processors

    Publication Year: 2000, Page(s):80 - 89
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    The 2-D discrete wavelet transform (DWT) suits image processing applications well, allowing for excellent compression. Many architectures have been proposed to perform the 1, 2 and 3-D DWT, but few address the precision necessary to ensure perfect reconstruction. The goal of this work is to experimentally determine the precision needed to store the results of a 2-D DWT without introducing round-of... View full abstract»

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  • Intelligent module descriptions in the implementation of software radios

    Publication Year: 2000, Page(s):693 - 702
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    This paper explains our experience in applying “higher” levels of abstraction for DSP based designs. Higher levels of abstraction allow us to describe digital radio designs in a more generic fashion, abstracted over carrier frequencies and data rates. As such, specific instances of the radios can be compiled from our generic descriptions. In this way, we obtain rapid reconfiguration wi... View full abstract»

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  • Model based video segmentation

    Publication Year: 2000, Page(s):120 - 129
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    With the fast growth of video resources, efficient video classification and management are becoming more and more important. Video partitioning is a key issue in video classification. The video partitioning involves the detection of boundaries between uninterrupted segments (video shots) of scenes. Shot boundaries can be classified into two categories, gradual transition and instantaneous change (... View full abstract»

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  • A VLSI architecture for lifting-based wavelet transform

    Publication Year: 2000, Page(s):70 - 79
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    The discrete wavelet transform (DWT) is the basis for many image compression techniques, such as the upcoming JEPG2000. Lifting-based DWT requires fewer computations compared to the traditional convolution-based approach. In this paper, we propose a VLSI architecture to compute lifting-based 2D DWT, for a set of seven filters recommended in the JPEG2000 verification model. The architecture produce... View full abstract»

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  • High performance code generation for VLIW digital signal processors

    Publication Year: 2000, Page(s):683 - 692
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    VLIW (Very Long Instruction Word) architecture has been widely adopted in latest digital signal processor designs to meet the ever increasing need of computing power in, e.g. multimedia applications. In this paper, we present an efficient and retargetable code generation tool for VLIW based DSPs. To make the code generation tool retargetable, we first developed a versatile coding constraint model ... View full abstract»

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  • Error resilient video transmission with adaptive stream-shuffling and bi-directional error concealment

    Publication Year: 2000, Page(s):33 - 42
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    This paper proposes a set of resident algorithms in conjunction with the H.263 standard to support video transmission over mobile radio channels. Specifically, an adaptive stream-shuffling scheme is proposed to mitigate the effects of burst-errors in mobile channels, while an efficient error detection and a bi-directional error concealment algorithm, which exploits the inherent correlation and the... View full abstract»

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  • Low-power signal processing via error-cancellation

    Publication Year: 2000, Page(s):553 - 562
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    We present an algorithmic noise-tolerance (ANT) technique for designing low-power DSP systems. The proposed technique achieves substantial energy savings via voltage overscaling, whereby the supply voltage is scaled beyond the minimum supply voltage Vdd-crit at which the architecture operates correctly for a given throughput specification. The resulting input-dependent soft errors are c... View full abstract»

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  • Hough transform algorithm for FPGA implementation

    Publication Year: 2000, Page(s):384 - 393
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    A novel algorithm for computing the Hough transform (HT) is introduced. The basic idea consists in using a combination of an incremental method with the usual HT expression to join circuit performance and accuracy requirements. The algorithm is primarily developed to fit field programmable gate arrays (FPGA) implementation that have become a competitive alternative for high performance digital sig... View full abstract»

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  • Fast shape decoding for MPEG-4 video

    Publication Year: 2000, Page(s):110 - 119
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    To achieve fast shape decoding in MPEG-4, it is necessary to have a high speed binary shape decoder. A fast architecture is presented here that is able to decode up to 72.4 Mpixels/s, meeting up to MPEG-4 Main Profile @ Level 3 real time requirement. High performance is achieved by using a lookahead scheme in the probability generation unit and a fast ALU. Simpler shift registers are used in place... View full abstract»

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  • A comparative analysis for low power motion estimation VLSI architectures

    Publication Year: 2000, Page(s):149 - 158
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    The power consumption is very critical for portable video applications. The largest portion of power is consumed in the motion estimation module, as it requires a huge amount of computations. This paper compares different full-search motion estimation architectures targeted for low power consumption. Each of the architectures is analyzed, and then compared to the others. An architectural enhanceme... View full abstract»

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  • Low power 2-D array VLSI architecture for block matching motion estimation using computation suspension

    Publication Year: 2000, Page(s):60 - 69
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    We propose a low power 2-D array VLSI architecture for block matching motion estimation based on computation suspension. A portion of the processing elements can be disabled adaptively during the computation of the sum of absolute difference (SAD) of a candidate block when the partial SAD obtained so far is found larger than the current minimum SAD to save power. An efficient VLSI architecture whi... View full abstract»

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  • An architecture for a power-aware distributed microsensor node

    Publication Year: 2000, Page(s):581 - 590
    Cited by:  Papers (44)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    Networks of distributed microsensors are emerging as a compelling solution for a wide range of data gathering applications. Perhaps the most substantial challenge facing designers of small but long-lived microsensor nodes is the need for significant reductions in energy consumption. We propose a power-aware design methodology that emphasizes the graceful scalability of energy consumption with fact... View full abstract»

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  • Efficient transmission of triangle meshes to graphics processors

    Publication Year: 2000, Page(s):275 - 284
    Cited by:  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    The performance of VLSI graphics processors is rising rapidly with the incorporation of specialized 3D geometry processing hardware into the graphics accelerator. Due to memory and bus bandwidth limitations, host systems often cannot deliver geometric data to graphics processors fast enough to saturate their processing capability. This paper proposes a compression scheme designed to alleviate the ... View full abstract»

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  • VLSI implementation of a low-energy soft digital filter

    Publication Year: 2000, Page(s):437 - 446
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    In this paper, we present a VLSI implementation of an energy-efficient digital filtering algorithm developed using the soft DSP framework. Soft DSP refers to overscaling the supply voltage without sacrificing speed and employing algorithmic error-control to restore the resulting performance degradation. It is shown that delay imbalance at the circuit level inherent in existing arithmetic structure... View full abstract»

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  • Systematic consolidation of input and output buffers in synchronous dataflow specifications

    Publication Year: 2000, Page(s):673 - 682
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    Synchronous Dataflow, a subset of dataflow, is a commonly used model of computation in block diagram DSP programming environments. Because of the limited amount of memory in embedded DSPs, a key problem during software synthesis from SDF specifications is the minimization of the memory used by the target code. We develop a powerful formal technique called buffer merging that attempts to overlay bu... View full abstract»

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  • A single-chip video signal processing system with embedded DRAM

    Publication Year: 2000, Page(s):23 - 32
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    A programmable single-chip multiprocessor system for video signal processing applications has been developed. It integrates four processing nodes with on-chip DRAM and application-specific interfaces. The embedded DRAM is primarily used as a frame buffer and makes external memory for most applications obsolete. For fast access to local data segments a static RAM is also integrated in each processi... View full abstract»

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  • Area estimation for DSP algorithms

    Publication Year: 2000, Page(s):623 - 632
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    In this paper we present a method to estimate the layout area of DSP algorithms that are designed using the standard cell methodology. The circuit description is given as a netlist of standard cell library modules. The area occupied by the circuit can be estimated prior to the actual layout phase. Area estimation before final layout is important for design evaluation and for the prediction of the ... View full abstract»

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  • Optimized MAP turbo decoder

    Publication Year: 2000, Page(s):245 - 254
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    The very powerful turbo codes are a breakthrough in coding theory. The implementation of the iterative turbo decoder however hampers their incorporation in real systems. We tackle this problem by optimizing the decoder on two levels: the separate decoder modules and the global decoder system. Our module level optimizations greatly reduce the decoding delay and energy. The main contribution of this... View full abstract»

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  • Extended time handling strategies for the improvement of prediction accuracy in event driven power estimation

    Publication Year: 2000, Page(s):539 - 552
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    This paper presents a methodology for calculating very accurate mean power estimates for integrated digital CMOS circuits at gate level. It is shown that by means of improving the time and history handling algorithm of an event driven simulation system can increase the accuracy of predicted power consumption up to 20% compared to a previous, highly efficient method. The outlined approach is capabl... View full abstract»

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  • A high performance FPGA implementation of DES

    Publication Year: 2000, Page(s):374 - 383
    Cited by:  Papers (6)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    FPGAs have proven to be very effective and efficient devices on which to implement encryption algorithms. They perform at much faster data-rates and provide better security than equivalent software implementations. They also provide more flexibility than ASIC implementations. This paper presents a high performance silicon intellectual property (IP) core for the data encryption standard (DES) encry... View full abstract»

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  • Standardized video interface eases design process and reduces time-to-market

    Publication Year: 2000, Page(s):100 - 109
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    Video ICs are composed of several signal processing units that perform different tasks such as filtering, changing the sampling rate or mixing different data streams. In most cases these blocks are connected to form a processing chain, where one block receives signals from the preceding one. To develop an IC more effectively, it is desired to reuse the known cores. The design of several video ICs ... View full abstract»

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