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Sixteenth International Symposium on Quality Electronic Design

2-4 March 2015

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Displaying Results 1 - 25 of 125
  • [Front cover]

    Publication Year: 2015, Page(s): 1
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  • [Title page]

    Publication Year: 2015, Page(s): 1
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  • [Copyright notice]

    Publication Year: 2015, Page(s): 1
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  • Welcome

    Publication Year: 2015, Page(s): 1
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  • Best Paper candidates & ISQED 2015 Best Papers

    Publication Year: 2015, Page(s):2 - 3
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  • ISQED 2015 Fellow Award

    Publication Year: 2015, Page(s):4 - 5
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  • Organizing committee

    Publication Year: 2015, Page(s):6 - 11
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  • General information

    Publication Year: 2015, Page(s):13 - 15
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  • Program at a glance

    Publication Year: 2015, Page(s): 16
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  • Innovotek [advertisement]

    Publication Year: 2015, Page(s): 1
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  • Corporate sponsors

    Publication Year: 2015, Page(s): 1
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  • Call for papers

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  • Table of contents

    Publication Year: 2015, Page(s):1 - 8
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  • Stack based sense amplifier designs for reducing input-referred offset

    Publication Year: 2015, Page(s):1 - 4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (498 KB) | HTML iconHTML

    The design of high performance SRAM in scaled technology nodes has become challenging due to an increase in both variation and leakage. The sense amplifier is one component that is particularly sensitive to threshold voltage variation due to its symmetrical design. Reducing the intrinsic input-referred offset of the sense amp reduces the bitline development time, which improves both energy and del... View full abstract»

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  • Designing low-VTh STT-RAM for write energy reduction in scaled technologies

    Publication Year: 2015, Page(s):5 - 9
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (165 KB) | HTML iconHTML

    This paper investigates the use of extremely low threshold voltage (VTh) for the select transistor in STT-RAM cell. While doing so intuitively improves its write margin, the extra current can also result in an MTJ oxide breakdown in the selected cell, as well as higher leakage current in an unselected cell inducing a false write in it. We thus propose an all-digital write driver to bias... View full abstract»

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  • High-performance and high-yield 5 nm underlapped FinFET SRAM design using P-type access transistors

    Publication Year: 2015, Page(s):10 - 17
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (598 KB) | HTML iconHTML

    In this paper, different characteristics of SRAM cells based on 5 nm underlapped FinFET technology are studied. For the cell structures, which make use of P type access transistors and pre-discharging bitlines to “0” during the read operation, the read current and write margin (WM) are improved. In addition, 8T structures with less underlap for write access transistors are suggested.... View full abstract»

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  • An energy-efficient on-chip memory structure for variability-aware near-threshold operation

    Publication Year: 2015, Page(s):23 - 28
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (162 KB) | HTML iconHTML

    On-chip memory is one of the most energy consuming components in processors. Aggressive voltage scaling to the sub-/near-threshold region is thus applied even to the memory used for ultra-low power applications. In this paper, an energy-efficient cell-based memory structure which is stably working with a near-threshold operating voltage is proposed. The circuit simulation using a commercial 28-nm ... View full abstract»

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  • Thermal sensor allocation for SoCs based on temperature gradients

    Publication Year: 2015, Page(s):29 - 34
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (706 KB) | HTML iconHTML

    Recently, numerous techniques have been proposed so that the temperature distribution of a chip can be managed dynamically during its operation, and these dynamic thermal management (DTM) schemes rely on on-chip thermal sensors in order to get the accurate temperature information. The challenging question is how to allocate a proper number of sensors on a die in order to get the accurate thermal i... View full abstract»

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  • Clock skew optimization for maximizing time margin by utilizing flexible flip-flop timing

    Publication Year: 2015, Page(s):35 - 39
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1094 KB) | HTML iconHTML

    Clock skew scheduling is one of the essential steps to be carefully performed during the design process. Two commonly used strategies for solving the task are the scheduling of clock arrival times under bounded clock skew constraint and the scheduling of clock arrival times under hold and setup time constraints. This work belongs to the useful clock skew scheduling. In comparison with the prior wo... View full abstract»

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  • Large-scale multi-corner leakage optimization under the sign-off timing environment

    Publication Year: 2015, Page(s):40 - 45
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (358 KB) | HTML iconHTML

    In this paper, we present an efficient algorithm for large-scale leakage optimization under sign-off timing constraints using the technique of multiple voltage threshold (multi-Vt) assignment. Several practical considerations are addressed, such as the synergistic propagation of swaps across all sign-off timing corners, iterative application of block-level and interface logic model (ILM)-level swa... View full abstract»

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  • Fast obstacle-avoiding octilinear steiner minimal tree construction algorithm for VLSI design

    Publication Year: 2015, Page(s):46 - 50
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (671 KB) | HTML iconHTML

    With advance in manufacturing technology, 45° and 135° diagonal segments can be permitted in an octilinear routing model. In this article, we present a heuristic algorithm to solve obstacle-avoiding octilinear Steiner minimal tree (OAOSMT) construction problem. We first construct an obstacle-free Euclidean minimal spanning tree (OFEMST). Then two lookup tables about OFEMST's edge are... View full abstract»

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  • A router for via configurable structured ASIC with standard cells and relocatable IPs

    Publication Year: 2015, Page(s):51 - 56
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (259 KB) | HTML iconHTML

    This article presents a router, called Rover II, for via-configurable structured ASIC with mixed standard cells and relocatable IPs. Rover II extends the work of Rover and incorporates a porting of NTHU-Route 2.0 and NCTU-GR global routers. Experimental results show that Rover II can successfully route a via-configurable structured ASIC with standard cells and IPs under different routing fabrics. ... View full abstract»

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  • Circuit design perspectives for Ge FinFET at 10nm and beyond

    Publication Year: 2015, Page(s):57 - 60
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1005 KB) | HTML iconHTML

    In this paper we study the circuit design implications of Ge vs. Si PMOS FinFETs at the 10 and 7nm nodes, using TCAD calibrated statistical compact models and the ARM predictive benchmarking flow. The ARM predictive flow incorporates advanced-node-relevant layouts, design rules, parasitic RC extraction and wire-loading. We present the first comprehensive simulation study evaluating Ge pFinFETs in ... View full abstract»

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  • Electrical characteristic and power consumption fluctuations of trapezoidal bulk FinFET devices and circuits induced by random line edge roughness

    Publication Year: 2015, Page(s):61 - 64
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (863 KB) | HTML iconHTML

    In this work, we use an experimentally calibrated 3D quantum-mechanically-corrected device simulation to study different types of line edge roughness (LER) on the DC/AC and digital circuit characteristic variability of 14-nm-gate HKMG trapezoidal bulk FinFETs. By using a time-domain Gaussian noise function as the LER-profile generator, we compare four types of LER: fin-LER inclusive of resist-LER ... View full abstract»

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  • Study of the impact of aging on many-core energy-efficient DSP systems

    Publication Year: 2015, Page(s):66 - 70
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    During the normal operational use, integrated circuits go through what is popularly known as wearout or aging. At system level, aging causes gradual speed degradation of the design over their service life. In a many-core homogeneous design and over a period of activity, this can lead to variation in speed depending on the workload distribution on cores. In the same design context, Voltage Scaling ... View full abstract»

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