Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541)

13-16 Sept. 2000

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  • Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541)

    Publication Year: 2000
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    Freely Available from IEEE
  • Author index

    Publication Year: 2000, Page(s):xv - xvi
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    Freely Available from IEEE
  • Capturing input switching dependency in crosstalk noise modeling

    Publication Year: 2000, Page(s):330 - 334
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (541 KB)

    Simulations of CMOS circuits for different input switching conditions reveal that the peak crosstalk noise can differ significantly for a given circuit structure with specific technology parameters and specific signal transition times. We show that these effects can be captured by appropriate victim driver modeling and we propose a systematic method to find the equivalent resistances for different... View full abstract»

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  • Efficient static timing analysis in presence of crosstalk

    Publication Year: 2000, Page(s):335 - 339
    Cited by:  Papers (8)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (593 KB)

    In this paper we show that iterative updating of timing windows is necessary when signals on the same path are mutually capacitively coupled. To improve the accuracy of timing analysis we use implications induced by functional irredundant path sensitization criteria. Experimental results have demonstrated the efficacy and efficiency of our proposed techniques. View full abstract»

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  • High-level synthesis and behavioral VHDL writing style towards a methodology for behavioral IP reuse

    Publication Year: 2000, Page(s):177 - 181
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    The recent emergence of commercial high-level synthesis tools raises the question of specifying IPs at the algorithmic, or behavioral, level. While flexibility of currently used soft IPs is limited to optimizing the logic synthesis flow, HLS introduces architectural flexibility and allows a closer adaptation to the requirements of a target application. Since reusing behavioral code may be hazardou... View full abstract»

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  • CD-ROM drive system

    Publication Year: 2000, Page(s):199 - 203
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    We have developed a front-end processor core that can be easily embedded into CD-ROM/DVD drive LSIs. Our new slice level feedback system and performance-driven optimization techniques enabled design of a 3.13 mm2, 64X-speed processor for CD-ROM drive. A test chip was implemented in 0.35 μm CMOS. Experimental results show that performance exceeds the requirements for 48X and potential... View full abstract»

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  • Dynamic-threshold CMOS SRAM cells for fast, portable applications

    Publication Year: 2000, Page(s):359 - 363
    Cited by:  Papers (13)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    A novel quad-rail CMOS SRAM cell architecture that doubles cell read current, improves cell static noise margin (SNM) by 70%, increases cell immunity to SER and lowers cell standby power by over an order of magnitude is proposed. These improvements are achieved by implementing a scheme of WL transition triggered pulses on source and substrate terminals of cell inverter transistors that share a com... View full abstract»

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  • Using computational RAM for volume rendering

    Publication Year: 2000, Page(s):253 - 257
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    The gap between processor speed and memory access time limits the performance of memory-intensive applications such as volume rendering. In this paper we compare the performance of stages of the splatting volume rendering algorithm on a workstation and on the Computational RAM (C·RAM) simulator. C·RAM is a Processor-in-Memory architecture, which integrates SIMD processing elements in... View full abstract»

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  • A layered approach to behavioral modeling of bus protocols

    Publication Year: 2000, Page(s):170 - 173
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    This paper presents a hierarchical approach to designing behavioral functional models (BFMs) for bus protocols, based on the protocols' defined hierarchies of data-transfer. Classical approaches to BFM design for bus protocols restrict themselves to the most rudimentary levels of data-exchange, leading to inefficient and error-prone modeling of higher level data transfers. This paper presents a la... View full abstract»

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  • Real time application architectural synthesis dedicated to sub-micron technologies

    Publication Year: 2000, Page(s):397 - 401
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    Architectural synthesis tools map algorithms to architectures under real time constraints and quickly provide estimations of area and performance. However, these tools do not take the VLSI circuit interconnection cost into account whereas this cost becomes predominant with the technology decrease and the application complexity increase. A new methodology that enables the interconnection cost to be... View full abstract»

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  • Development and application of a macro model for flash EEPROM design

    Publication Year: 2000, Page(s):192 - 196
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    The inclusion of embedded flash memory in systems-on-chip designs enables the addition of many new features. However to enable designers to embed flash memory in an efficient and competent manner, they must have the capability to simulate full circuit operation. Therefore a flexible flash EEPROM model is required. An accurate and numerically efficient model for the transient and DC characteristics... View full abstract»

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  • Formal representation of gated clock designs

    Publication Year: 2000, Page(s):352 - 356
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    The action systems formal framework has recently been applied to the area of asynchronous and synchronous VLSI design. In this paper, we present aspects of formal gated clock design. This proves useful when targeting mixed-architecture designs: devices composed of subsystems that operate in an asynchronous manner with respect to each other, even though some of them may have synchronous implementat... View full abstract»

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  • VLSI implementation of portable MPEG-4 audio decoder

    Publication Year: 2000, Page(s):80 - 84
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    VLSI implementation of an MPEG-4 audio decoder is described, which is dedicated to portable audio appliances. MPEG-4 audio surpasses conventional audio codec schemes in terms of sound quality and compression rate. Based on the results of sound quality evaluation, a low-power architecture is devised by means of frame-level pipeline and optimization of functional datapath. The proposed MPEG-4 audio ... View full abstract»

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  • Design self-synchronized clock distribution networks in an SoC ASIC using DLL with remote clock feedback

    Publication Year: 2000, Page(s):248 - 252
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    This paper presents an automatic clock skew control scheme in an SoC ASIC that inserts appropriated delays on the outputs of the clock generator such that the target module clocks MCK-1 through MCK-n are all in phase (or 1800 out of phase) with PLL's input system clock. The clock distribution network consists of multiple delay circuits with the remote feedback clock inputs, which insert different ... View full abstract»

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  • A reconfigurable pipelined IDCT for low-energy video processing

    Publication Year: 2000, Page(s):13 - 17
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    In video processing, average data rates are often significantly lower than a given maximum possible rate. Consequently, VLSI systems that are capable of processing video streams at the maximum data rates specified in video standards can be excessively dissipative at low data rates. Such inefficiencies are particularly pronounced in heavily pipelined designs, in which registers account for the bulk... View full abstract»

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  • Characterization of interconnect coupling noise using in-situ delay-change curve measurements

    Publication Year: 2000, Page(s):321 - 325
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    The delay-change curve (DCC) characterizes the variation of the interconnect delay due to coupling noise. This paper describes a set of novel models that relate the DCC to the coupling noise waveform. These models are targeted for use in the timing margin design and accurate experimental determination of sub-nanosecond coupling noise. The circuit structure, a set of measurements, the model equatio... View full abstract»

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  • Designing reusable components in VHDL

    Publication Year: 2000, Page(s):165 - 169
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    Hardware Description Languages (HDLs) are commonly used to construct hardware systems. Reuse of the designs is common practice to improve the productivity. The HDLs allow the creation of reusable models, but design disciplines are required to reach an efficient reusable design, because the reusability of a design does not come with language features alone. Analysis of the reusability in VHDL appli... View full abstract»

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  • Coupling aware routing

    Publication Year: 2000, Page(s):392 - 396
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    In this paper, we develop methods to reduce interconnect delay and noise caused by coupling. First, we introduce two novel problems that deal with coupling-the Coupling-Free Routing (CFR) Problem and the Maximum Coupling-Free Layout (MAX-CFL) Problem. We argue that these problems are useful in both global and detailed routing. Then, we develop algorithms to efficiently solve the problems. Our expe... View full abstract»

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  • Optimization of a 0.13 μm CMOS backend interconnect process for ASIC SOC: low K dielectric vs. Cu conductor

    Publication Year: 2000, Page(s):114 - 118
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    A backend optimization scheme for a 0.13 μm CMOS process is illustrated based on a set of performance and process metrics. Performance is measured against manufacturing risk and expense with a focus on the requirements for ASIC/SOC. In evaluating how to effectively optimize 0.13 μm high performance ASIC/SOC, we compared two technology enhancements-Cu and low K. The results demonstrate that l... View full abstract»

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  • Methodology and code reuse in the verification of telecommunication SOCs

    Publication Year: 2000, Page(s):187 - 191
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    Rapid developments in semiconductor technologies have opened a broad spectrum of opportunities for the telecommunication industry to produce complex systems from a number of predesigned cores on a single chip. System-on-Chip (SOC) designs bring new verification challenges that become critical issues under the `time-to-market' pressure. The reuse of verification code and methodology is a major fact... View full abstract»

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  • Model reductions in MDG-based model checking

    Publication Year: 2000, Page(s):347 - 351
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    Multiway Decision Graphs (MDG) can symbolically represent abstract state machines (ASM). Since there is no preimage operation in MDG due to the presence of abstract state variables, all backward reduction algorithms can not be used in MDG. In this paper we propose a simple but powerful way to construct a reduced abstract transition system derived from the original ASM by using only the transition ... View full abstract»

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  • Blind estimation and error correction in a CMOS ADC

    Publication Year: 2000, Page(s):124 - 128
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    For small integrated CMOS digital chips that communicate via analog signals the size and the cost of the AD-converters is a problem. An integrated CMOS AD-converter that could be built into the chip would solve this problem. In a CMOS process, the manufacturers only guarantee a very low accuracy of the resistances. The components of the ADC are therefore very inaccurate. The purpose here is to pre... View full abstract»

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  • Low level watermarking of VLSI designs for intellectual property protection

    Publication Year: 2000, Page(s):136 - 140
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    We propose a method for watermarking, called “fingermarking”, for integrated circuit design at the physical design level. The watermark is embedded in the transistor layout, making our method applicable to digital, analog, and mixed-signal SOC designs. We show that a robust watermark can be applied to many designs, and can be implemented with little or no cost in circuit area or perfor... View full abstract»

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  • Vector quantization processor for mobile video communication

    Publication Year: 2000, Page(s):75 - 79
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    A vector quantization processor suitable for video communication has been developed. It performs 10 frames/sec of encoding and decoding QCIF with the FRMSHVQ algorithm. It consumes 49 mW at 25 MHz. The chip is fabricated in a 0.35 μm CMOS technology View full abstract»

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  • Low power VLSI prototype for motion tracking architecture

    Publication Year: 2000, Page(s):243 - 247
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    This paper presents a low power VLSI prototype for a video object motion tracking architecture that can be used for very low bit rate online video applications. The architecture prototypes a 2D mesh-based video object motion tracking algorithm. It can be used as a building block for 2D mesh-based video object systems such as MPEG-4 and MPEG-7 systems. Moreover, the power consumption and the delay ... View full abstract»

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