2014 Formal Methods in Computer-Aided Design (FMCAD)

21-24 Oct. 2014

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  • [Front cover]

    Publication Year: 2014, Page(s): 1
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  • [Title page]

    Publication Year: 2014, Page(s): 1
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  • [Copyright notice]

    Publication Year: 2014, Page(s): 1
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  • Preface

    Publication Year: 2014, Page(s):i - ii
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  • Organization committee

    Publication Year: 2014, Page(s):iii - v
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  • Table of contents

    Publication Year: 2014, Page(s):vii - viii
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  • Challenging problems in industrial formal verification

    Publication Year: 2014, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (77 KB)

    Summary form only given. The electronic design industry has emerged in the recent years to adopt the system-on-chip (SoC) design methodology, where systems become a smart and complex integration of many configurable and reusable intellectual properties (IP) designs such as CPU, GPU, DSP, etc. SoC design methodologies have become common to a wide range of systems, starting from high-end servers, do... View full abstract»

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  • Challenges in bit-precise reasoning

    Publication Year: 2014, Page(s): 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (77 KB)

    Summary form only given. Bit-precise reasoning (BPR) precisely captures the semantics of systems down to each individual bit and thus is essential to many verification and synthesis tasks for both hardware and software systems. As an instance of Satisfiabiliy Modulo Theories (SMT), BPR is in essence about word-level decision procedures for the theory of bit-vectors. In practice, quantiers and othe... View full abstract»

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  • Efficient symbolic execution for software testing

    Publication Year: 2014, Page(s): 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (121 KB)

    Summary form only given. Symbolic execution has proven to be a practical technique for building automated test case generation and bug finding tools. While the basic technique had been introduced already in the 70s, the advent of modern SAT and SMT solvers has lead to a surge of tools and techniques in the area over the last decade. This tutorial will introduce and compare the different approaches... View full abstract»

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  • A tour of CVC4: How it works, and how to use it

    Publication Year: 2014, Page(s): 7
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (77 KB)

    CVC4 is a solver for Satisfiability Modulo Theories (SMT). This tutorial aims to give participants an overview of SMT, describe the main features of CVC4, and walk through in-depth examples using CVC4 to demonstrate how to solve real problems with an SMT solver. We will provide a detailed description of various aspects of CVC4's internals, including its architecture, its capacity for dealing with ... View full abstract»

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  • Compiler verification for fun and profit

    Publication Year: 2014, Page(s): 9
    Cited by:  Papers (1)
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  • Computer-aided verification technology for biology

    Publication Year: 2014, Page(s): 11
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  • The FMCAD 2014 graduate student forum

    Publication Year: 2014, Page(s): 13
    Cited by:  Papers (2)
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  • Response property checking via distributed state space exploration

    Publication Year: 2014, Page(s):15 - 22
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (780 KB) | HTML iconHTML

    A response property is a simple liveness property that, given state predicates p and q, asserts "whenever a p-state is visited, a g-state will be visited in the future". This paper presents an efficient and scalable implementation for explicit-state model of checking response properties on systems with strongly- and weakly-fair actions, using a network of machines. Our approach is a novel twist on... View full abstract»

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  • Towards Pareto-optimal parameter synthesis for monotonie cost functions

    Publication Year: 2014, Page(s):23 - 30
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (749 KB) | HTML iconHTML

    Designers are often required to explore alternative solutions, trading off along different dimensions (e.g., power consumption, weight, cost, reliability, response time). Such exploration can be encoded as a problem of parameter synthesis, i.e., finding a parameter valuation (representing a design solution) such that the corresponding system satisfies a desired property. In this paper, we tackle t... View full abstract»

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  • SAT-based methods for circuit synthesis

    Publication Year: 2014, Page(s):31 - 34
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (674 KB) | HTML iconHTML

    Reactive synthesis supports designers by automatically constructing correct hardware from declarative specifications. Synthesis algorithms usually compute a strategy, and then construct a circuit that implements it. In this work, we study SAT- and QBF-based methods for the second step, i.e., computing circuits from strategies. This includes methods based on QBF-certification, interpolation, and co... View full abstract»

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  • Synthesis of synchronization using uninterpreted functions

    Publication Year: 2014, Page(s):35 - 42
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (750 KB) | HTML iconHTML

    Correctness of a program with respect to concurrency is often hard to achieve, but easy to specify: the concurrent program should produce the same results as a sequential reference version. We show how to automatically insert small atomic sections into a program to ensure correctness with respect to this implicit specification. Using techniques from bounded software model checking, we transform th... View full abstract»

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  • Interpolation with Guided Refinement: Revisiting incrementality in SAT-based unbounded model checking

    Publication Year: 2014, Page(s):43 - 50
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (550 KB) | HTML iconHTML

    This paper addresses model checking based on SAT solvers and Craig interpolants. We tackle major scalability problems of state-of-the-art interpolation-based approaches, and we achieve two main results: (1) a novel model checking algorithm; (2) a new and flexible way to handle an incremental representation of (over-approximated) forward reachable states. The new model checking algorithm (IGR: Inte... View full abstract»

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  • Efficient verification of periodic programs using sequential consistency and snapshots

    Publication Year: 2014, Page(s):51 - 58
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1245 KB) | HTML iconHTML

    We verify safety properties of periodic programs, consisting of periodically activated threads scheduled preemptively based on their priorities. We develop an approach based on generating, and solving, a provably correct verification condition (VC). The VC is generated by adapting Lamport's sequential consistency to the semantics of periodic programs. Our approach is able to handle periodic progra... View full abstract»

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  • Under-approximate flowpipes for non-linear continuous systems

    Publication Year: 2014, Page(s):59 - 66
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (763 KB) | HTML iconHTML

    We propose an approach for computing under- as well as over-approximations for the reachable sets of continuous systems which are defined by non-linear Ordinary Differential Equations (ODEs). Given a compact and connected initial set of states, described by a system of polynomial inequalities, we compute under-approximations of the set of states reachable over time. Our approach is based on a simp... View full abstract»

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  • Disproving termination with overapproximation

    Publication Year: 2014, Page(s):67 - 74
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (554 KB) | HTML iconHTML

    When disproving termination using known techniques (e.g. recurrence sets), abstractions that overapproximate the program's transition relation are unsound. In this paper we introduce live abstractions, a natural class of abstractions that can be combined with the recent concept of closed recurrence sets to soundly disprove termination. To demonstrate the practical usefulness of this new approach w... View full abstract»

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  • Faster temporal reasoning for infinite-state programs

    Publication Year: 2014, Page(s):75 - 82
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (793 KB) | HTML iconHTML

    In this paper, we describe a new symbolic model checking procedure for CTL verification of infinite-state programs. Our procedure exploits the natural decomposition of the state space given by the control-flow graph in combination with the nesting of temporal operators to optimize reasoning performed during symbolic model checking. An experimental evaluation against competing tools demonstrates th... View full abstract»

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  • Template-based circuit understanding

    Publication Year: 2014, Page(s):83 - 90
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1360 KB) | HTML iconHTML

    When verifying or reverse-engineering digital circuits, one often wants to identify and understand small components in a larger system. A possible approach is to show that the sub-circuit under investigation is functionally equivalent to a reference implementation. In many cases, this task is difficult as one may not have full information about the mapping between input and output of the two circu... View full abstract»

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  • Simulation and formal verification of x86 machine-code programs that make system calls

    Publication Year: 2014, Page(s):91 - 98
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (549 KB) | HTML iconHTML

    We present an approach to modeling and verifying machine-code programs that exhibit non-determinism. Specifically, we add support for system calls to our formal, executable model of the user-level x86 instruction-set architecture (ISA). The resulting model, implemented in the ACL2 theorem-proving system, allows both formal analysis and efficient simulation of x86 machine-code programs; the logical... View full abstract»

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  • DRUPing for interpolates

    Publication Year: 2014, Page(s):99 - 106
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (542 KB) | HTML iconHTML

    We present a method for interpolation based on DRUP proofs. Interpolants are widely used in model checking, synthesis and other applications. Most interpolation algorithms rely on a resolution proof produced by a SAT-solver for unsatisfaible formulas. The proof is traversed and translated into an interpolant by replacing resolution steps with AND and OR gates. This process is efficient (once there... View full abstract»

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