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Memory Technology, Design and Testing, 2000. Records of the 2000 IEEE International Workshop on

Date 8-8 Aug. 2000

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  • 2000 IEEE International Workshop On Hemorq Technology Design And Testing

    Publication Year: 2000, Page(s):iii - vii
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    Freely Available from IEEE
  • Proceedings 2000. International Workshop on Parallel Processing

    Publication Year: 2000
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    Freely Available from IEEE
  • Author index

    Publication Year: 2000, Page(s): 131
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    Freely Available from IEEE
  • Defect analysis and realistic fault model extensions for static random access memories

    Publication Year: 2000, Page(s):119 - 124
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Resistive short defects were injected in the sense amplifier, memory cells and the address decoder of an SRAM memory. The behavior of these defects were examined using a transistor-level simulation framework. An unbalanced sense amplifier fault, consisting of a resistive short injected in the pull-down path of a sense amplifier, was examined. The scope of this type of fault could be broadened to c... View full abstract»

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  • Hierarchical sector biasing organization for flash memories

    Publication Year: 2000, Page(s):29 - 33
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    In Flash memories, separate biasing of the source line and, in the case of a triple well process, of the well terminals of each sector, is required to prevent electrical stress of unselected sectors. This paper presents a hierarchical biasing architecture developed for this purpose. The lines carrying the voltages to be applied to the terminals of all the sectors in the same row are routed horizon... View full abstract»

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  • Windowed MRAM sensing scheme

    Publication Year: 2000, Page(s):47 - 55
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    Memories using any type of on-chip magnetic memory elements (often known as MRAM) sometimes suffer from unstable magnetic domains within the memory bits. These states may occur because of improper bit manufacturing techniques or transient magnetic fields generated on or off chip. In many cases these errors are actually correctable if this unstable domain situation can be detected. In any tradition... View full abstract»

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  • Fast voltage regulator for multilevel flash memories

    Publication Year: 2000, Page(s):34 - 38
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    This paper presents a very fast recovery voltage regulator for large capacitive loads in multilevel (ML) Flash memories. A suitable low-power structure limits positive output overshoots during transients, thereby allowing the basic regulation loop to be designed for very high recovery speed. The circuit is therefore able to quickly restore the output voltage to its regulated value when a previousl... View full abstract»

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  • Design techniques for embedded EEPROM memories in portable ASIC and ASSP solutions

    Publication Year: 2000, Page(s):39 - 44
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    Design techniques for embedded EEPROM memories working under a wide supply voltage range are described. First, a current controlled ring oscillator for stable programming pulse generation has been developed. For supply voltage values ranging from 2 ν to 3.5 ν, in the [-40°C-85°C] industrial temperature range, less than 30% of oscillation period variation has been measured. Moreover, ... View full abstract»

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  • Diagnosing the interconnect of bus-connected multi-RAM systems under restricted and general fault models

    Publication Year: 2000, Page(s):14 - 19
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    This paper presents new approaches for detection and diagnosis (with no confounding or aliasing) of interconnect faults (short, open and stuck-at) in a system consisting of multiple RAM chips connected through busses. These systems (referred to as a bus-connected multi RAM systems, or BCMRS) are characterized by multiple types of lines (bus and driver lines), disjoint busses (address and data) as ... View full abstract»

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  • A low voltage embedded single port SRAM generator in a 0.18 μm standard CMOS process

    Publication Year: 2000, Page(s):106 - 110
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    A low voltage embedded single port SRAM memory generator implemented in a 6 metals, 0.18 μm standard CMOS process is described. The typical (8k×16) cut achieves 300 MHz maximum frequency, with a 3.3 ns access time at 1.3 V and 25°C and a typical power of 60 μA/MHz at 1.3 V. Special care has been taken to reduce the standby current as well. The hierarchical wordline architecture, an... View full abstract»

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  • Tutorial: synchronous dynamic memory test construction-a field approach

    Publication Year: 2000, Page(s):59 - 64
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    This paper gives an introduction how to construct dynamic memory tests and test flows. Step by step a basic march test is developed choosing a pattern, voltage levels and timings. Starting with this basic pattern, modifications for characterization, diagnostic and speed testing are discussed. These variations are then used to construct a test sequence to ensure functionality according to the data ... View full abstract»

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  • 66 MHz 2.3 M ternary dynamic content addressable memory

    Publication Year: 2000, Page(s):101 - 105
    Cited by:  Papers (13)  |  Patents (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    This paper describes a 66 MHz 2.3 M Content Addressable Memory (CAM) which uses DRAM technology for the basic ternary CAM cell. The chip's architecture allows a high speed search operation and single cycle learning. The DRAM based cell structure enables implementation of a larger table size than is available in similar technology SRAM based CAMs. A new matchline sense amplifier allows fast, low po... View full abstract»

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  • Using GLFSRs for pseudo-random memory BIST

    Publication Year: 2000, Page(s):85 - 90
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    We present the application of Generalized Linear Feedback Shift Registers (GLFSRs) for generation of patterns for pseudo-random memory built-in self-test (BIST). Recently, it was shown that using GLFSRs as pattern generators for pseudo-random logic tests can increase the fault coverage noticeably in comparison to standard pseudo-random test pattern generators. Since memory faults differ from logic... View full abstract»

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  • Optimizing memory bandwidth with ILP based memory exploration and assignment for low power embedded systems

    Publication Year: 2000, Page(s):95 - 100
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    In this paper, we describe a low power memory design procedure that optimizes memory bandwidth in VLSI sytems. We develop the procedures of loop transformation to optimize the memory cost for the required storage bandwidth. Next, we develop memory assignment based on ILP model that is derived from mapping graph (MG) such that we can find (i) the best memory configuration (minimum-area memory confi... View full abstract»

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  • A simple built-in self test for dual ported SRAMs

    Publication Year: 2000, Page(s):79 - 84
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    This paper presents a discussion on a simple memory Built-In Self Test (BIST) design for dual ported SRAM that concurrently applies a modified March test to both ports of an embedded SRAM. It begins by outlining the role of embedded dual ported SRAM in today's ASICs., briefly discusses how commercial memory test tools deal with dual ported SRAMs and the difficulties to realistically cover the comp... View full abstract»

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  • Failure mechanisms in semiconductor memory circuits

    Publication Year: 2000, Page(s):7 - 13
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (812 KB)

    This tutorial will describe the physical failure mechanisms that commonly occur in memory and other microcircuits. There will be a general introduction to reliability concepts and definitions. The tutorial will follow a physics of failure approach, emphasizing cause and cure, rather than a statistical reliability. Many of the failure mechanisms affecting memories are general to other microcircuits... View full abstract»

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  • Diagnostic testing of embedded memories based on output tracing

    Publication Year: 2000, Page(s):113 - 118
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    A new approach to diagnostic testing of embedded memories is presented which enables the design of tests that provide complete detection and distinguishing of all faults in a given fault model. The approach is based on decomposition of functional memory faults into basic fault effects and output tracing. Output tracing involves storing all read operation results for defective memory cells and repl... View full abstract»

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  • March tests for realistic faults in two-port memories

    Publication Year: 2000, Page(s):73 - 78
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    This paper starts with an overview of realistic faults models for two-port memories, divided into single-port faults and unique two-port faults. The latter faults can not be detected with the conventional single-port memory tests; they require special tests. Thereafter the paper presents a set of four march tests detecting the unique two-port faults. Three of the tests have a time complexity of &t... View full abstract»

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  • Optimizing memory tests by analyzing defect coverage

    Publication Year: 2000, Page(s):20 - 25
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    This paper describes how analyzing the defect coverage of memory tests can lead to optimized test coverage and rest application time before the device reaches production. A 9-port embedded SRAM will be used as the example memory for this paper. We will analyze four different functional tests and show that using just two of the four tests provides nearly all the defect coverage of all four tests, b... View full abstract»

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  • Yield analysis methodology for low defectivity wafer fabs

    Publication Year: 2000, Page(s):65 - 69
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    It is well known that the yield of an integrated circuit can be modeled based on random defect density. In state-of-the-art wafer fabs, continuous defect reduction is a high engineering priority, and as a result they indeed achieve entitlement values for the defect density, as determined by the design rules, equipment set, and their facility characteristics. Even if a wafer fab achieves its entitl... View full abstract»

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