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Memory Technology, Design and Testing, 2000. Records of the 2000 IEEE International Workshop on

Date 8-8 Aug. 2000

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  • 2000 IEEE International Workshop On Hemorq Technology Design And Testing

    Page(s): iii - vii
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    Freely Available from IEEE
  • Proceedings 2000. International Workshop on Parallel Processing

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    Freely Available from IEEE
  • Author index

    Page(s): 131
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    Freely Available from IEEE
  • Fast voltage regulator for multilevel flash memories

    Page(s): 34 - 38
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    This paper presents a very fast recovery voltage regulator for large capacitive loads in multilevel (ML) Flash memories. A suitable low-power structure limits positive output overshoots during transients, thereby allowing the basic regulation loop to be designed for very high recovery speed. The circuit is therefore able to quickly restore the output voltage to its regulated value when a previously discharged capacitance is connected to its output. Typical applications include read word-line and program bit-line voltage regulators for ML Flash memories, where accurate and quickly regulated voltages are vital for optimal read and program operations. Computer simulations for a 0.18 μm 2 bit/cell 64 Mb Flash memory are shown View full abstract»

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  • Diagnostic testing of embedded memories based on output tracing

    Page(s): 113 - 118
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    A new approach to diagnostic testing of embedded memories is presented which enables the design of tests that provide complete detection and distinguishing of all faults in a given fault model. The approach is based on decomposition of functional memory faults into basic fault effects and output tracing. Output tracing involves storing all read operation results for defective memory cells and replaces the commonly used evaluation of a “fail” signal. In particular, we examine memory tests of linear order (O(N)), since this class of tests requires low test application times and is realizable as built-in self-test circuitry with very low area overhead View full abstract»

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  • 66 MHz 2.3 M ternary dynamic content addressable memory

    Page(s): 101 - 105
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    This paper describes a 66 MHz 2.3 M Content Addressable Memory (CAM) which uses DRAM technology for the basic ternary CAM cell. The chip's architecture allows a high speed search operation and single cycle learning. The DRAM based cell structure enables implementation of a larger table size than is available in similar technology SRAM based CAMs. A new matchline sense amplifier allows fast, low power sensing of the matchline. Among the chip's many features are a DDR input interface and the ability to cascade up to eight parts without additional logic. The density and speed of this part make it suitable for many applications such as network switching View full abstract»

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  • Diagnosing the interconnect of bus-connected multi-RAM systems under restricted and general fault models

    Page(s): 14 - 19
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    This paper presents new approaches for detection and diagnosis (with no confounding or aliasing) of interconnect faults (short, open and stuck-at) in a system consisting of multiple RAM chips connected through busses. These systems (referred to as a bus-connected multi RAM systems, or BCMRS) are characterized by multiple types of lines (bus and driver lines), disjoint busses (address and data) as well as by the presence of memories (whose number is given by D). Detection and maximal diagnosis are considered under a restricted fault model (short faults only) as well as a general fault model (all types of faults) View full abstract»

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  • Optimizing memory tests by analyzing defect coverage

    Page(s): 20 - 25
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    This paper describes how analyzing the defect coverage of memory tests can lead to optimized test coverage and rest application time before the device reaches production. A 9-port embedded SRAM will be used as the example memory for this paper. We will analyze four different functional tests and show that using just two of the four tests provides nearly all the defect coverage of all four tests, but requires a fraction of the test application time. We will also show that a more complete test set should contain non-simultaneous port accesses and time-dependent tests View full abstract»

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  • Failure mechanisms in semiconductor memory circuits

    Page(s): 7 - 13
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    This tutorial will describe the physical failure mechanisms that commonly occur in memory and other microcircuits. There will be a general introduction to reliability concepts and definitions. The tutorial will follow a physics of failure approach, emphasizing cause and cure, rather than a statistical reliability. Many of the failure mechanisms affecting memories are general to other microcircuits as well. The failure mechanisms will be split into three areas. Failures of the assembly and packaging, failures of the interconnects and the remainder of the die, and failures of the transistors View full abstract»

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  • Design techniques for embedded EEPROM memories in portable ASIC and ASSP solutions

    Page(s): 39 - 44
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    Design techniques for embedded EEPROM memories working under a wide supply voltage range are described. First, a current controlled ring oscillator for stable programming pulse generation has been developed. For supply voltage values ranging from 2 ν to 3.5 ν, in the [-40°C-85°C] industrial temperature range, less than 30% of oscillation period variation has been measured. Moreover, this oscillator can be completely turned off in stand-by mode for power saving concern. Techniques for read optimization under the constraints of portable systems are also addressed. First, the advantage of using two oxide thickness advanced process for logic delay optimization of EEPROM memories is evaluated, and the gain obtained using the ATMEL 56.8 K mixed memory, 0.35 μm digital process is reported. Then, a word line boosting technique used to amplify the available memory cell current is described. Thanks to the boost, current sensing delay remains acceptable even for supply voltage values under 2 ν. In addition, address transition detection (ATD) based cut off circuitry is used to minimize the power consumption at higher values of the supply voltage. A 32 k×16, 1.8 ν-3.3 ν embedded memory has been designed using the proposed techniques. 170 ns typical access time (290 ns in process and temperature worst case) has been simulated at 1.8 ν, with an average current consumption lower than 3 mA at 3.3 ν when reading at 3.3 MHz frequency View full abstract»

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  • A low voltage embedded single port SRAM generator in a 0.18 μm standard CMOS process

    Page(s): 106 - 110
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    A low voltage embedded single port SRAM memory generator implemented in a 6 metals, 0.18 μm standard CMOS process is described. The typical (8k×16) cut achieves 300 MHz maximum frequency, with a 3.3 ns access time at 1.3 V and 25°C and a typical power of 60 μA/MHz at 1.3 V. Special care has been taken to reduce the standby current as well. The hierarchical wordline architecture, and a differential output bus allow low power characteristics. At the same time high speed is reached, especially thanks to a novel dynamic wordline decoder. The generator ranges from 1 Kbit to 2 Mbit and features an optional programmable redundancy View full abstract»

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  • Optimizing memory bandwidth with ILP based memory exploration and assignment for low power embedded systems

    Page(s): 95 - 100
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    In this paper, we describe a low power memory design procedure that optimizes memory bandwidth in VLSI sytems. We develop the procedures of loop transformation to optimize the memory cost for the required storage bandwidth. Next, we develop memory assignment based on ILP model that is derived from mapping graph (MG) such that we can find (i) the best memory configuration (minimum-area memory configuration if power is bound or minimum-power memory configuration if area is bound) and (ii) the power/area efficient array assignment to given memory library (the number of memory banks, the number of ports, and the total memory size) View full abstract»

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  • Windowed MRAM sensing scheme

    Page(s): 47 - 55
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    Memories using any type of on-chip magnetic memory elements (often known as MRAM) sometimes suffer from unstable magnetic domains within the memory bits. These states may occur because of improper bit manufacturing techniques or transient magnetic fields generated on or off chip. In many cases these errors are actually correctable if this unstable domain situation can be detected. In any traditional sensing method that only detects 1 or 0 states, these unstable states usually increase the soft-error-rate (SER) in that they reduce the bit related signal although the bits may still function to some degree. In other cases, these domain instabilities may render a bit unusable. In either case, if this situation is not detected it could easily result in erroneous memory operation. We have developed a Windowed Sensing Scheme described here to address this problem, which allows bits with unstable domains to be detected during reading. It also allows for improved sensing error rate by identifying read cycles with inadequate signal size caused for example by external noise View full abstract»

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  • March tests for realistic faults in two-port memories

    Page(s): 73 - 78
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    This paper starts with an overview of realistic faults models for two-port memories, divided into single-port faults and unique two-port faults. The latter faults can not be detected with the conventional single-port memory tests; they require special tests. Thereafter the paper presents a set of four march tests detecting the unique two-port faults. Three of the tests have a time complexity of θ(n) and one of θ (√n), whereby n is the size of the two-port memory cell array. Two of the four tests have been implemented at Intel and applied to 1500 two-port memories passing all single port tests. The test results show that two dies fail to pass the implemented tests, which means that the tests are superior View full abstract»

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  • Using GLFSRs for pseudo-random memory BIST

    Page(s): 85 - 90
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    We present the application of Generalized Linear Feedback Shift Registers (GLFSRs) for generation of patterns for pseudo-random memory built-in self-test (BIST). Recently, it was shown that using GLFSRs as pattern generators for pseudo-random logic tests can increase the fault coverage noticeably in comparison to standard pseudo-random test pattern generators. Since memory faults differ from logic faults, we examined if that is also the case for pseudo-random memory tests. We found that GLFSRs can increase the fault coverage of pseudo-random tests for several fault types, especially for complex faults as stuck-open faults. Thus, the usage of GLFSRs as pattern generators for pseudo-random memory testing is recommended although some area overhead has to be accepted View full abstract»

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  • Defect analysis and realistic fault model extensions for static random access memories

    Page(s): 119 - 124
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    Resistive short defects were injected in the sense amplifier, memory cells and the address decoder of an SRAM memory. The behavior of these defects were examined using a transistor-level simulation framework. An unbalanced sense amplifier fault, consisting of a resistive short injected in the pull-down path of a sense amplifier, was examined. The scope of this type of fault could be broadened to cover any type of defect that makes the right and left side of the sense amplifier to become asymmetric. The effects of resistive shorts in the pull-up and pulldown path of a memory cell were examined. For the defects in the pull-up path, the effectiveness of different test methods designed to detect this type of defects were examined. The pause method is effective for resistive defects with large values while the weak write DfT method can detect small defects by introducing structural changes to the memory cell. In the case of a defect in the pull-down path of the memory cell, two consecutive read operations were determined to be the most effective solution to detect these defects. Three types of defects were injected in the dynamic logic address decoder. The defects affecting the pulldown and the input to the N-FETs manifested themselves as the address decoder selects more than one or zero memory cell. The defects affecting the restore unit and the word address line resulted in not selecting any cell in the memory. The injected defects in the restore unit could not be detected without the addition of DfT logic to the unit View full abstract»

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  • Yield analysis methodology for low defectivity wafer fabs

    Page(s): 65 - 69
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    It is well known that the yield of an integrated circuit can be modeled based on random defect density. In state-of-the-art wafer fabs, continuous defect reduction is a high engineering priority, and as a result they indeed achieve entitlement values for the defect density, as determined by the design rules, equipment set, and their facility characteristics. Even if a wafer fab achieves its entitlement defect density, a comprehensive yield analysis methodology is still required not only to identify any yield excursions, but also to continually find ways for further yield improvements. Whereas in a wafer fab with defect density above its entitlement value, the yield analysis methodology can easily be focussed on defect density reduction alone, in the low defectivity wafer fabs different approach needs to be adopted. In this paper we discuss yield analysis methodologies appropriate for low defectivity wafer fabs View full abstract»

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  • A simple built-in self test for dual ported SRAMs

    Page(s): 79 - 84
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    This paper presents a discussion on a simple memory Built-In Self Test (BIST) design for dual ported SRAM that concurrently applies a modified March test to both ports of an embedded SRAM. It begins by outlining the role of embedded dual ported SRAM in today's ASICs., briefly discusses how commercial memory test tools deal with dual ported SRAMs and the difficulties to realistically cover the complex coupling faults which are suspected to expose memory errors at the system level. Subsequently this paper examines the MARCH test for modification to enable the development of a simple BIST architecture that can be designed for concurrent testing of both ports with minimum extra cost View full abstract»

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  • Tutorial: synchronous dynamic memory test construction-a field approach

    Page(s): 59 - 64
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    This paper gives an introduction how to construct dynamic memory tests and test flows. Step by step a basic march test is developed choosing a pattern, voltage levels and timings. Starting with this basic pattern, modifications for characterization, diagnostic and speed testing are discussed. These variations are then used to construct a test sequence to ensure functionality according to the data sheet specification View full abstract»

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  • Hierarchical sector biasing organization for flash memories

    Page(s): 29 - 33
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    In Flash memories, separate biasing of the source line and, in the case of a triple well process, of the well terminals of each sector, is required to prevent electrical stress of unselected sectors. This paper presents a hierarchical biasing architecture developed for this purpose. The lines carrying the voltages to be applied to the terminals of all the sectors in the same row are routed horizontally nearby the respective row. A vertical line controls the connection of the terminals of all sectors in the same column to the required bias lines. The proposed biasing organization allows silicon area saving thanks to simplified routing and reduced number of high voltage switches. The presented biasing architecture has been successfully used in a 64-Mbit 2-bit/cell NOR-type Flash memory and has been integrated in 0.18 μm CMOS fabrication process View full abstract»

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