Date 12-12 July 2000
Filter Results
Displaying Results 1 - 25 of 35
-
Author index
|
PDF (43 KB)
-
Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors
|
PDF (184 KB)
-
Integration of high-performance ASICs into reconfigurable systems providing additional multimedia functionality
|
PDF (292 KB)
-
-
-
-
-
Subword permutation instructions for two-dimensional multimedia processing in MicroSIMD architectures
|
PDF (224 KB)
-
-
-
-
Block-update parallel processing QRD-RLS algorithm for throughput improvement with low power consumption
|
PDF (440 KB)
-
-
Efficient VLSI architectures for baseband signal processing in wireless base-station receivers
|
PDF (260 KB)
-
-
-
-
-
A 108 Gbps, 1.5 GHz 1D-DCT architecture
|
PDF (248 KB)
-
-
A new algorithm for the elimination of common subexpressions in hardware implementation of digital filters by using genetic programming
|
PDF (1084 KB)
-
-
-
Control for high-speed PE arrays
|
PDF (356 KB)
-


