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2014 IEEE 22nd Annual Symposium on High-Performance Interconnects

26-28 Aug. 2014

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Displaying Results 1 - 25 of 29
  • [Title page i]

    Publication Year: 2014, Page(s): i
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  • [Title page iii]

    Publication Year: 2014, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2014, Page(s): iv
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  • Table of contents

    Publication Year: 2014, Page(s):v - vi
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  • Message from the General Co-Chairs

    Publication Year: 2014, Page(s):vii - viii
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  • Message from the Technical Program Chairs

    Publication Year: 2014, Page(s): ix
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  • Organizing Committee

    Publication Year: 2014, Page(s): x
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  • Steering Committee

    Publication Year: 2014, Page(s): xi
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  • Technical Program Committee

    Publication Year: 2014, Page(s): xii
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  • Tutorial reviewers

    Publication Year: 2014, Page(s): xiii
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  • Keynotes

    Publication Year: 2014, Page(s):xiv - xix
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (101 KB)

    Provides an abstract for each of the keynote presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Invited Talks

    Publication Year: 2014, Page(s):xx - xxii
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    Provides an abstract for each of the invited presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Executive Roundtable

    Publication Year: 2014, Page(s): xxiii
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  • VC Forum

    Publication Year: 2014, Page(s): xxiv
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (69 KB)

    Summary form only given, as follows. Title: Fireside Chat with Matthew Palmer, Partner at Wiretap Ventures. Moderators: Michael Howard, Co-founder and Principal Analyst, Infonetics Research View full abstract»

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  • Tutorials [4 abstracts]

    Publication Year: 2014, Page(s):xxv - xxix
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    Provides an abstract for each of the tutorial presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Acknowledgements

    Publication Year: 2014, Page(s): xxx
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  • Modeling and Evaluation of Chip-to-Chip Scale Silicon Photonic Networks

    Publication Year: 2014, Page(s):1 - 8
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB) | HTML iconHTML

    Silicon photonic interconnects have been proposed as a solution to address chip I/O communication bottlenecks in multicore architectures. In this paper, we perform comprehensive design exploration of inter-chip photonic links and networking architectures. Because the energy efficiencies of such architectures have been shown to be highly sensitive to link utilization, our design exploration covers ... View full abstract»

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  • Accelerating Spark with RDMA for Big Data Processing: Early Experiences

    Publication Year: 2014, Page(s):9 - 16
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB) | HTML iconHTML

    Apache Hadoop Map Reduce has been highly successful in processing large-scale, data-intensive batch applications on commodity clusters. However, for low-latency interactive applications and iterative computations, Apache Spark, an emerging in-memory processing framework, has been stealing the limelight. Recent studies have shown that current generation Big Data frameworks (like Hadoop) cannot effi... View full abstract»

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  • End-to-End Adaptive Packet Aggregation for High-Throughput I/O Bus Network Using Ethernet

    Publication Year: 2014, Page(s):17 - 24
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (369 KB) | HTML iconHTML

    Input/output (I/O) bus networks using Ethernets transfer a PCI Express (PCIe) I/O packet between a host and an I/O device by encapsulating it into an Ethernet frame. Because the size of PCIe packets is generally small in such systems, the overhead to individually encapsulate them into Ethernet frames lowers the PCIe throughput provided by Ethernet connections. This decrease in throughput directly ... View full abstract»

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  • Strategies for Mitigating TCAM Space Bottlenecks

    Publication Year: 2014, Page(s):25 - 32
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (378 KB) | HTML iconHTML

    Transport networks satisfy requests to forward data in a given topology. At the level of a network element, forwarding decisions are defined by flows. To implement desired data properties during forwarding, a network operator imposes economic models by applying policies to flows. In real applications, the number of different policies is much smaller than the number of flows. In this work, we draw ... View full abstract»

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  • The Buffer Size vs Link Bandwidth Tradeoff in Lossless Networks

    Publication Year: 2014, Page(s):33 - 40
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (393 KB) | HTML iconHTML

    Data center networks demand high bandwidth switches. These networks also sustain common in cast scenarios, which require large switch buffers. Therefore, network and switch designers encounter a buffer-bandwidth trade off as follows. Large switch buffers allow absorbing larger in cast workload. However, higher switch bandwidth allows both faster buffer draining and more link pausing, which reduces... View full abstract»

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  • Quasi Fat Trees for HPC Clouds and Their Fault-Resilient Closed-Form Routing

    Publication Year: 2014, Page(s):41 - 48
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (719 KB) | HTML iconHTML

    High-Performance Computing (HPC) Clusters and Data Center Networks often rely on fat-tree topologies. However, fat trees and their known variants are not designed for concurrent small jobs. As a result, in recent years, HPC designers have introduced ad-hoc topologies to offer better performance for these concurrent small jobs. In this paper, we present and formally define these topologies, which w... View full abstract»

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  • Reuse Distance Based Circuit Replacement in Silicon Photonic Interconnection Networks for HPC

    Publication Year: 2014, Page(s):49 - 56
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (885 KB) | HTML iconHTML

    Optical interconnects, which support the transport of large bandwidths over warehouse-scale distance, can help to further scale data-movement capabilities in high performance computing (HPC) platforms. However, due to the circuit switching nature of optical systems and additional peculiarities, such as sensitivity to temperature and the need for wavelength channel locking, optical links generally ... View full abstract»

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  • The Tofu Interconnect 2

    Publication Year: 2014, Page(s):57 - 62
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (822 KB) | HTML iconHTML

    The Tofu Interconnect 2 (Tofu2) is a system interconnect designed for the successor model of the FUJITSU Supercomputer PRIME HPC FX10. Tofu2 uses a 25 Gbps transmission technology that is about two times faster than those of existing HPC interconnects, and uses optical transceivers in an extremely high ratio. Despite the major change of physical transport medium, Tofu2 inherits and enhances the fe... View full abstract»

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  • Characterizing Traffic Locality in 3D NoC-Based CMPs Using a Path-Based Partitioning Method

    Publication Year: 2014, Page(s):63 - 70
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1158 KB) | HTML iconHTML

    The incorporation of the third dimension in the design of Networks-on-Chip (NoCs) provides a major performance improvement for Chip Multi-Processors (CMPs). Since multicast communication is necessary for parallelization, it is of significant importance to design routing methods that support multicast. The partitioning strategy has a major impact on the efficiency of the multicast routing method. T... View full abstract»

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